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[RISCV] Reduce the number of parameters to copyPhysRegVector. NFC (#70502)
The Lmul and SubRegIdx can be derived from the opcode. Make NF default to 1.
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-80
lines changed

2 files changed

+87
-80
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 86 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -294,40 +294,52 @@ static bool isConvertibleToVMV_V_V(const RISCVSubtarget &STI,
294294
return false;
295295
}
296296

297-
void RISCVInstrInfo::copyPhysRegVector(
298-
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
299-
const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc,
300-
unsigned Opc, unsigned NF, RISCVII::VLMUL LMul, unsigned SubRegIdx) const {
297+
void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock &MBB,
298+
MachineBasicBlock::iterator MBBI,
299+
const DebugLoc &DL, MCRegister DstReg,
300+
MCRegister SrcReg, bool KillSrc,
301+
unsigned Opc, unsigned NF) const {
301302
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
302303

304+
RISCVII::VLMUL LMul;
305+
unsigned SubRegIdx;
306+
unsigned VVOpc, VIOpc;
307+
switch (Opc) {
308+
default:
309+
llvm_unreachable("Impossible LMUL for vector register copy.");
310+
case RISCV::VMV1R_V:
311+
LMul = RISCVII::LMUL_1;
312+
SubRegIdx = RISCV::sub_vrm1_0;
313+
VVOpc = RISCV::PseudoVMV_V_V_M1;
314+
VIOpc = RISCV::PseudoVMV_V_I_M1;
315+
break;
316+
case RISCV::VMV2R_V:
317+
LMul = RISCVII::LMUL_2;
318+
SubRegIdx = RISCV::sub_vrm2_0;
319+
VVOpc = RISCV::PseudoVMV_V_V_M2;
320+
VIOpc = RISCV::PseudoVMV_V_I_M2;
321+
break;
322+
case RISCV::VMV4R_V:
323+
LMul = RISCVII::LMUL_4;
324+
SubRegIdx = RISCV::sub_vrm4_0;
325+
VVOpc = RISCV::PseudoVMV_V_V_M4;
326+
VIOpc = RISCV::PseudoVMV_V_I_M4;
327+
break;
328+
case RISCV::VMV8R_V:
329+
assert(NF == 1);
330+
LMul = RISCVII::LMUL_8;
331+
SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
332+
VVOpc = RISCV::PseudoVMV_V_V_M8;
333+
VIOpc = RISCV::PseudoVMV_V_I_M8;
334+
break;
335+
}
336+
303337
bool UseVMV_V_V = false;
304338
bool UseVMV_V_I = false;
305339
MachineBasicBlock::const_iterator DefMBBI;
306340
if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
307341
UseVMV_V_V = true;
308-
// We only need to handle LMUL = 1/2/4/8 here because we only define
309-
// vector register classes for LMUL = 1/2/4/8.
310-
unsigned VIOpc;
311-
switch (LMul) {
312-
default:
313-
llvm_unreachable("Impossible LMUL for vector register copy.");
314-
case RISCVII::LMUL_1:
315-
Opc = RISCV::PseudoVMV_V_V_M1;
316-
VIOpc = RISCV::PseudoVMV_V_I_M1;
317-
break;
318-
case RISCVII::LMUL_2:
319-
Opc = RISCV::PseudoVMV_V_V_M2;
320-
VIOpc = RISCV::PseudoVMV_V_I_M2;
321-
break;
322-
case RISCVII::LMUL_4:
323-
Opc = RISCV::PseudoVMV_V_V_M4;
324-
VIOpc = RISCV::PseudoVMV_V_I_M4;
325-
break;
326-
case RISCVII::LMUL_8:
327-
Opc = RISCV::PseudoVMV_V_V_M8;
328-
VIOpc = RISCV::PseudoVMV_V_I_M8;
329-
break;
330-
}
342+
Opc = VVOpc;
331343

332344
if (DefMBBI->getOpcode() == VIOpc) {
333345
UseVMV_V_I = true;
@@ -351,38 +363,39 @@ void RISCVInstrInfo::copyPhysRegVector(
351363
MIB.addReg(RISCV::VL, RegState::Implicit);
352364
MIB.addReg(RISCV::VTYPE, RegState::Implicit);
353365
}
354-
} else {
355-
int I = 0, End = NF, Incr = 1;
356-
unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
357-
unsigned DstEncoding = TRI->getEncodingValue(DstReg);
358-
unsigned LMulVal;
359-
bool Fractional;
360-
std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
361-
assert(!Fractional && "It is impossible be fractional lmul here.");
362-
if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
363-
I = NF - 1;
364-
End = -1;
365-
Incr = -1;
366-
}
366+
return;
367+
}
367368

368-
for (; I != End; I += Incr) {
369-
auto MIB = BuildMI(MBB, MBBI, DL, get(Opc),
370-
TRI->getSubReg(DstReg, SubRegIdx + I));
371-
if (UseVMV_V_V)
372-
MIB.addReg(TRI->getSubReg(DstReg, SubRegIdx + I), RegState::Undef);
373-
if (UseVMV_V_I)
374-
MIB = MIB.add(DefMBBI->getOperand(2));
375-
else
376-
MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I),
377-
getKillRegState(KillSrc));
378-
if (UseVMV_V_V) {
379-
const MCInstrDesc &Desc = DefMBBI->getDesc();
380-
MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
381-
MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
382-
MIB.addImm(0); // tu, mu
383-
MIB.addReg(RISCV::VL, RegState::Implicit);
384-
MIB.addReg(RISCV::VTYPE, RegState::Implicit);
385-
}
369+
int I = 0, End = NF, Incr = 1;
370+
unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
371+
unsigned DstEncoding = TRI->getEncodingValue(DstReg);
372+
unsigned LMulVal;
373+
bool Fractional;
374+
std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
375+
assert(!Fractional && "It is impossible be fractional lmul here.");
376+
if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
377+
I = NF - 1;
378+
End = -1;
379+
Incr = -1;
380+
}
381+
382+
for (; I != End; I += Incr) {
383+
auto MIB =
384+
BuildMI(MBB, MBBI, DL, get(Opc), TRI->getSubReg(DstReg, SubRegIdx + I));
385+
if (UseVMV_V_V)
386+
MIB.addReg(TRI->getSubReg(DstReg, SubRegIdx + I), RegState::Undef);
387+
if (UseVMV_V_I)
388+
MIB = MIB.add(DefMBBI->getOperand(2));
389+
else
390+
MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I),
391+
getKillRegState(KillSrc));
392+
if (UseVMV_V_V) {
393+
const MCInstrDesc &Desc = DefMBBI->getDesc();
394+
MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
395+
MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
396+
MIB.addImm(0); // tu, mu
397+
MIB.addReg(RISCV::VL, RegState::Implicit);
398+
MIB.addReg(RISCV::VTYPE, RegState::Implicit);
386399
}
387400
}
388401
}
@@ -460,92 +473,88 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
460473

461474
// VR->VR copies.
462475
if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
463-
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
464-
/*NF=*/1, RISCVII::LMUL_1, RISCV::sub_vrm1_0);
476+
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V);
465477
return;
466478
}
467479

468480
if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {
469-
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V,
470-
/*NF=*/1, RISCVII::LMUL_2, RISCV::sub_vrm1_0);
481+
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V);
471482
return;
472483
}
473484

474485
if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) {
475-
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV4R_V,
476-
/*NF=*/1, RISCVII::LMUL_4, RISCV::sub_vrm1_0);
486+
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV4R_V);
477487
return;
478488
}
479489

480490
if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) {
481-
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV8R_V,
482-
/*NF=*/1, RISCVII::LMUL_8, RISCV::sub_vrm1_0);
491+
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV8R_V);
483492
return;
484493
}
485494

486495
if (RISCV::VRN2M1RegClass.contains(DstReg, SrcReg)) {
487496
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
488-
/*NF=*/2, RISCVII::LMUL_1, RISCV::sub_vrm1_0);
497+
/*NF=*/2);
489498
return;
490499
}
491500

492501
if (RISCV::VRN2M2RegClass.contains(DstReg, SrcReg)) {
493502
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V,
494-
/*NF=*/2, RISCVII::LMUL_2, RISCV::sub_vrm2_0);
503+
/*NF=*/2);
495504
return;
496505
}
497506

498507
if (RISCV::VRN2M4RegClass.contains(DstReg, SrcReg)) {
499508
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV4R_V,
500-
/*NF=*/2, RISCVII::LMUL_4, RISCV::sub_vrm4_0);
509+
/*NF=*/2);
501510
return;
502511
}
503512

504513
if (RISCV::VRN3M1RegClass.contains(DstReg, SrcReg)) {
505514
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
506-
/*NF=*/3, RISCVII::LMUL_1, RISCV::sub_vrm1_0);
515+
/*NF=*/3);
507516
return;
508517
}
509518

510519
if (RISCV::VRN3M2RegClass.contains(DstReg, SrcReg)) {
511520
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V,
512-
/*NF=*/3, RISCVII::LMUL_2, RISCV::sub_vrm2_0);
521+
/*NF=*/3);
513522
return;
514523
}
515524

516525
if (RISCV::VRN4M1RegClass.contains(DstReg, SrcReg)) {
517526
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
518-
/*NF=*/4, RISCVII::LMUL_1, RISCV::sub_vrm1_0);
527+
/*NF=*/4);
519528
return;
520529
}
521530

522531
if (RISCV::VRN4M2RegClass.contains(DstReg, SrcReg)) {
523532
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V,
524-
/*NF=*/4, RISCVII::LMUL_2, RISCV::sub_vrm2_0);
533+
/*NF=*/4);
525534
return;
526535
}
527536

528537
if (RISCV::VRN5M1RegClass.contains(DstReg, SrcReg)) {
529538
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
530-
/*NF=*/5, RISCVII::LMUL_1, RISCV::sub_vrm1_0);
539+
/*NF=*/5);
531540
return;
532541
}
533542

534543
if (RISCV::VRN6M1RegClass.contains(DstReg, SrcReg)) {
535544
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
536-
/*NF=*/6, RISCVII::LMUL_1, RISCV::sub_vrm1_0);
545+
/*NF=*/6);
537546
return;
538547
}
539548

540549
if (RISCV::VRN7M1RegClass.contains(DstReg, SrcReg)) {
541550
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
542-
/*NF=*/7, RISCVII::LMUL_1, RISCV::sub_vrm1_0);
551+
/*NF=*/7);
543552
return;
544553
}
545554

546555
if (RISCV::VRN8M1RegClass.contains(DstReg, SrcReg)) {
547556
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
548-
/*NF=*/8, RISCVII::LMUL_1, RISCV::sub_vrm1_0);
557+
/*NF=*/8);
549558
return;
550559
}
551560

‎llvm/lib/Target/RISCV/RISCVInstrInfo.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,6 @@
1313
#ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
1414
#define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
1515

16-
#include "MCTargetDesc/RISCVBaseInfo.h"
1716
#include "RISCVRegisterInfo.h"
1817
#include "llvm/CodeGen/TargetInstrInfo.h"
1918
#include "llvm/IR/DiagnosticInfo.h"
@@ -67,8 +66,7 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
6766
void copyPhysRegVector(MachineBasicBlock &MBB,
6867
MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
6968
MCRegister DstReg, MCRegister SrcReg, bool KillSrc,
70-
unsigned Opc, unsigned NF, RISCVII::VLMUL LMul,
71-
unsigned SubRegIdx) const;
69+
unsigned Opc, unsigned NF = 1) const;
7270
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
7371
const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
7472
bool KillSrc) const override;

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