[RISCV] Reduce the number of parameters to copyPhysRegVector. NFC

[topperc]

The Lmul and SubRegIdx can be derived from the opcode.

Make NF default to 1.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

Changes

The Lmul and SubRegIdx can be derived from the opcode.

Make NF default to 1.

---

Full diff: https://github.com/llvm/llvm-project/pull/70502.diff

2 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+86-77)
• (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.h (+1-3)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 9e4e86100a2115b..a75a298132bfbc2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -294,40 +294,52 @@ static bool isConvertibleToVMV_V_V(const RISCVSubtarget &STI,
   return false;
 }
 
-void RISCVInstrInfo::copyPhysRegVector(
-    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
-    const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc,
-    unsigned Opc, unsigned NF, RISCVII::VLMUL LMul, unsigned SubRegIdx) const {
+void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock &MBB,
+                                       MachineBasicBlock::iterator MBBI,
+                                       const DebugLoc &DL, MCRegister DstReg,
+                                       MCRegister SrcReg, bool KillSrc,
+                                       unsigned Opc, unsigned NF) const {
   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 
+  RISCVII::VLMUL LMul;
+  unsigned SubRegIdx;
+  unsigned VVOpc, VIOpc;
+  switch (Opc) {
+  default:
+    llvm_unreachable("Impossible LMUL for vector register copy.");
+  case RISCV::VMV1R_V:
+    LMul = RISCVII::LMUL_1;
+    SubRegIdx = RISCV::sub_vrm1_0;
+    VVOpc = RISCV::PseudoVMV_V_V_M1;
+    VIOpc = RISCV::PseudoVMV_V_I_M1;
+    break;
+  case RISCV::VMV2R_V:
+    LMul = RISCVII::LMUL_2;
+    SubRegIdx = RISCV::sub_vrm2_0;
+    VVOpc = RISCV::PseudoVMV_V_V_M2;
+    VIOpc = RISCV::PseudoVMV_V_I_M2;
+    break;
+  case RISCV::VMV4R_V:
+    LMul = RISCVII::LMUL_4;
+    SubRegIdx = RISCV::sub_vrm4_0;
+    VVOpc = RISCV::PseudoVMV_V_V_M4;
+    VIOpc = RISCV::PseudoVMV_V_I_M4;
+    break;
+  case RISCV::VMV8R_V:
+    assert(NF == 1);
+    LMul = RISCVII::LMUL_8;
+    SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
+    VVOpc = RISCV::PseudoVMV_V_V_M8;
+    VIOpc = RISCV::PseudoVMV_V_I_M8;
+    break;
+  }
+
   bool UseVMV_V_V = false;
   bool UseVMV_V_I = false;
   MachineBasicBlock::const_iterator DefMBBI;
   if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
     UseVMV_V_V = true;
-    // We only need to handle LMUL = 1/2/4/8 here because we only define
-    // vector register classes for LMUL = 1/2/4/8.
-    unsigned VIOpc;
-    switch (LMul) {
-    default:
-      llvm_unreachable("Impossible LMUL for vector register copy.");
-    case RISCVII::LMUL_1:
-      Opc = RISCV::PseudoVMV_V_V_M1;
-      VIOpc = RISCV::PseudoVMV_V_I_M1;
-      break;
-    case RISCVII::LMUL_2:
-      Opc = RISCV::PseudoVMV_V_V_M2;
-      VIOpc = RISCV::PseudoVMV_V_I_M2;
-      break;
-    case RISCVII::LMUL_4:
-      Opc = RISCV::PseudoVMV_V_V_M4;
-      VIOpc = RISCV::PseudoVMV_V_I_M4;
-      break;
-    case RISCVII::LMUL_8:
-      Opc = RISCV::PseudoVMV_V_V_M8;
-      VIOpc = RISCV::PseudoVMV_V_I_M8;
-      break;
-    }
+    Opc = VVOpc;
 
     if (DefMBBI->getOpcode() == VIOpc) {
       UseVMV_V_I = true;
@@ -351,38 +363,39 @@ void RISCVInstrInfo::copyPhysRegVector(
       MIB.addReg(RISCV::VL, RegState::Implicit);
       MIB.addReg(RISCV::VTYPE, RegState::Implicit);
     }
-  } else {
-    int I = 0, End = NF, Incr = 1;
-    unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
-    unsigned DstEncoding = TRI->getEncodingValue(DstReg);
-    unsigned LMulVal;
-    bool Fractional;
-    std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
-    assert(!Fractional && "It is impossible be fractional lmul here.");
-    if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
-      I = NF - 1;
-      End = -1;
-      Incr = -1;
-    }
+    return;
+  }
 
-    for (; I != End; I += Incr) {
-      auto MIB = BuildMI(MBB, MBBI, DL, get(Opc),
-                         TRI->getSubReg(DstReg, SubRegIdx + I));
-      if (UseVMV_V_V)
-        MIB.addReg(TRI->getSubReg(DstReg, SubRegIdx + I), RegState::Undef);
-      if (UseVMV_V_I)
-        MIB = MIB.add(DefMBBI->getOperand(2));
-      else
-        MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I),
-                         getKillRegState(KillSrc));
-      if (UseVMV_V_V) {
-        const MCInstrDesc &Desc = DefMBBI->getDesc();
-        MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc)));  // AVL
-        MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
-        MIB.addImm(0);                                            // tu, mu
-        MIB.addReg(RISCV::VL, RegState::Implicit);
-        MIB.addReg(RISCV::VTYPE, RegState::Implicit);
-      }
+  int I = 0, End = NF, Incr = 1;
+  unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
+  unsigned DstEncoding = TRI->getEncodingValue(DstReg);
+  unsigned LMulVal;
+  bool Fractional;
+  std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
+  assert(!Fractional && "It is impossible be fractional lmul here.");
+  if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
+    I = NF - 1;
+    End = -1;
+    Incr = -1;
+  }
+
+  for (; I != End; I += Incr) {
+    auto MIB =
+        BuildMI(MBB, MBBI, DL, get(Opc), TRI->getSubReg(DstReg, SubRegIdx + I));
+    if (UseVMV_V_V)
+      MIB.addReg(TRI->getSubReg(DstReg, SubRegIdx + I), RegState::Undef);
+    if (UseVMV_V_I)
+      MIB = MIB.add(DefMBBI->getOperand(2));
+    else
+      MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I),
+                       getKillRegState(KillSrc));
+    if (UseVMV_V_V) {
+      const MCInstrDesc &Desc = DefMBBI->getDesc();
+      MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc)));  // AVL
+      MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
+      MIB.addImm(0);                                            // tu, mu
+      MIB.addReg(RISCV::VL, RegState::Implicit);
+      MIB.addReg(RISCV::VTYPE, RegState::Implicit);
     }
   }
 }
@@ -460,92 +473,88 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
 
   // VR->VR copies.
   if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
-    copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
-                      /*NF=*/1, RISCVII::LMUL_1, RISCV::sub_vrm1_0);
+    copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V);
     return;
   }
 
   if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {
-    copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V,
-                      /*NF=*/1, RISCVII::LMUL_2, RISCV::sub_vrm1_0);
+    copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V);
     return;
   }
 
   if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) {
-    copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV4R_V,
-                      /*NF=*/1, RISCVII::LMUL_4, RISCV::sub_vrm1_0);
+    copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV4R_V);
     return;
   }
 
   if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) {
-    copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV8R_V,
-                      /*NF=*/1, RISCVII::LMUL_8, RISCV::sub_vrm1_0);
+    copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV8R_V);
     return;
   }
 
   if (RISCV::VRN2M1RegClass.contains(DstReg, SrcReg)) {
     copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
-                      /*NF=*/2, RISCVII::LMUL_1, RISCV::sub_vrm1_0);
+                      /*NF=*/2);
     return;
   }
 
   if (RISCV::VRN2M2RegClass.contains(DstReg, SrcReg)) {
     copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V,
-                      /*NF=*/2, RISCVII::LMUL_2, RISCV::sub_vrm2_0);
+                      /*NF=*/2);
     return;
   }
 
   if (RISCV::VRN2M4RegClass.contains(DstReg, SrcReg)) {
     copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV4R_V,
-                      /*NF=*/2, RISCVII::LMUL_4, RISCV::sub_vrm4_0);
+                      /*NF=*/2);
     return;
   }
 
   if (RISCV::VRN3M1RegClass.contains(DstReg, SrcReg)) {
     copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
-                      /*NF=*/3, RISCVII::LMUL_1, RISCV::sub_vrm1_0);
+                      /*NF=*/3);
     return;
   }
 
   if (RISCV::VRN3M2RegClass.contains(DstReg, SrcReg)) {
     copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V,
-                      /*NF=*/3, RISCVII::LMUL_2, RISCV::sub_vrm2_0);
+                      /*NF=*/3);
     return;
   }
 
   if (RISCV::VRN4M1RegClass.contains(DstReg, SrcReg)) {
     copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
-                      /*NF=*/4, RISCVII::LMUL_1, RISCV::sub_vrm1_0);
+                      /*NF=*/4);
     return;
   }
 
   if (RISCV::VRN4M2RegClass.contains(DstReg, SrcReg)) {
     copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V,
-                      /*NF=*/4, RISCVII::LMUL_2, RISCV::sub_vrm2_0);
+                      /*NF=*/4);
     return;
   }
 
   if (RISCV::VRN5M1RegClass.contains(DstReg, SrcReg)) {
     copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
-                      /*NF=*/5, RISCVII::LMUL_1, RISCV::sub_vrm1_0);
+                      /*NF=*/5);
     return;
   }
 
   if (RISCV::VRN6M1RegClass.contains(DstReg, SrcReg)) {
     copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
-                      /*NF=*/6, RISCVII::LMUL_1, RISCV::sub_vrm1_0);
+                      /*NF=*/6);
     return;
   }
 
   if (RISCV::VRN7M1RegClass.contains(DstReg, SrcReg)) {
     copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
-                      /*NF=*/7, RISCVII::LMUL_1, RISCV::sub_vrm1_0);
+                      /*NF=*/7);
     return;
   }
 
   if (RISCV::VRN8M1RegClass.contains(DstReg, SrcReg)) {
     copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
-                      /*NF=*/8, RISCVII::LMUL_1, RISCV::sub_vrm1_0);
+                      /*NF=*/8);
     return;
   }
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 13f1bd4127b12b7..b3ef538ac169631 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -13,7 +13,6 @@
 #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
 #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
 
-#include "MCTargetDesc/RISCVBaseInfo.h"
 #include "RISCVRegisterInfo.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/IR/DiagnosticInfo.h"
@@ -67,8 +66,7 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
   void copyPhysRegVector(MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
                          MCRegister DstReg, MCRegister SrcReg, bool KillSrc,
-                         unsigned Opc, unsigned NF, RISCVII::VLMUL LMul,
-                         unsigned SubRegIdx) const;
+                         unsigned Opc, unsigned NF = 1) const;
   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                    const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
                    bool KillSrc) const override;

[preames]

LGTM

I might be tempted to invert the lookup and pass the LMUL instead of the copy opcode for the LMUL.

[topperc]

LGTM

I might be tempted to invert the lookup and pass the LMUL instead of the copy opcode for the LMUL.

I thought about that. Mainly didn't because the LMUL needs a header to be included in RISCVInstrInfo.h