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arsenmarsenm
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AMDGPU: Replace undef phi inputs with poison in tests (#130267)
I think the chance of this changing the tests in meaningful ways is very low. This was perl with a few minor adjustments to a few tests that produce new undefs. Only one test had a minor codegen change with the switch, which I dropped from the change.
1 parent ecec7d1 commit 8ce612f

35 files changed

+93
-93
lines changed

‎llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ if.true:
2626
br label %endif
2727

2828
endif:
29-
%v = phi i32 [ %val, %if.true ], [ undef, %entry ]
29+
%v = phi i32 [ %val, %if.true ], [ poison, %entry ]
3030
ret i32 %v
3131
}
3232

@@ -49,7 +49,7 @@ entry:
4949
br i1 %c, label %if.true, label %endif
5050

5151
endif:
52-
%v = phi i32 [ %val, %if.true ], [ undef, %entry ]
52+
%v = phi i32 [ %val, %if.true ], [ poison, %entry ]
5353
ret i32 %v
5454

5555
if.true:
@@ -82,7 +82,7 @@ if.true:
8282
br label %endif
8383

8484
endif:
85-
%v = phi i32 [ %val, %if.true ], [ undef, %entry ]
85+
%v = phi i32 [ %val, %if.true ], [ poison, %entry ]
8686
ret i32 %v
8787
}
8888

@@ -114,7 +114,7 @@ if.true:
114114
br label %endif
115115

116116
endif:
117-
%v = phi i32 [ %val, %if.true ], [ undef, %entry ]
117+
%v = phi i32 [ %val, %if.true ], [ poison, %entry ]
118118
ret i32 %v
119119
}
120120

‎llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-break-large-phis.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -643,11 +643,11 @@ define amdgpu_kernel void @phi_v15i8_random_constant_init(<15 x i8> %in, ptr %ou
643643
; OPT-NEXT: br label [[FINALLY]]
644644
; OPT: finally:
645645
; OPT-NEXT: [[TMP0:%.*]] = phi <4 x i8> [ <i8 poison, i8 1, i8 2, i8 3>, [[THEN]] ], [ [[LARGEPHI_EXTRACTSLICE1]], [[ELSE]] ]
646-
; OPT-NEXT: [[TMP1:%.*]] = phi <4 x i8> [ <i8 4, i8 undef, i8 6, i8 7>, [[THEN]] ], [ [[LARGEPHI_EXTRACTSLICE3]], [[ELSE]] ]
646+
; OPT-NEXT: [[TMP1:%.*]] = phi <4 x i8> [ <i8 4, i8 poison, i8 6, i8 7>, [[THEN]] ], [ [[LARGEPHI_EXTRACTSLICE3]], [[ELSE]] ]
647647
; OPT-NEXT: [[TMP2:%.*]] = phi <4 x i8> [ <i8 9, i8 10, i8 11, i8 12>, [[THEN]] ], [ [[LARGEPHI_EXTRACTSLICE5]], [[ELSE]] ]
648648
; OPT-NEXT: [[TMP3:%.*]] = phi i8 [ 13, [[THEN]] ], [ [[LARGEPHI_EXTRACTSLICE7]], [[ELSE]] ]
649649
; OPT-NEXT: [[TMP4:%.*]] = phi i8 [ 14, [[THEN]] ], [ [[LARGEPHI_EXTRACTSLICE9]], [[ELSE]] ]
650-
; OPT-NEXT: [[TMP5:%.*]] = phi i8 [ undef, [[THEN]] ], [ [[LARGEPHI_EXTRACTSLICE11]], [[ELSE]] ]
650+
; OPT-NEXT: [[TMP5:%.*]] = phi i8 [ poison, [[THEN]] ], [ [[LARGEPHI_EXTRACTSLICE11]], [[ELSE]] ]
651651
; OPT-NEXT: [[LARGEPHI_INSERTSLICE0:%.*]] = call <15 x i8> @llvm.vector.insert.v15i8.v4i8(<15 x i8> poison, <4 x i8> [[TMP0]], i64 0)
652652
; OPT-NEXT: [[LARGEPHI_INSERTSLICE1:%.*]] = call <15 x i8> @llvm.vector.insert.v15i8.v4i8(<15 x i8> [[LARGEPHI_INSERTSLICE0]], <4 x i8> [[TMP1]], i64 4)
653653
; OPT-NEXT: [[LARGEPHI_INSERTSLICE2:%.*]] = call <15 x i8> @llvm.vector.insert.v15i8.v4i8(<15 x i8> [[LARGEPHI_INSERTSLICE1]], <4 x i8> [[TMP2]], i64 8)
@@ -666,7 +666,7 @@ define amdgpu_kernel void @phi_v15i8_random_constant_init(<15 x i8> %in, ptr %ou
666666
; NOOPT-NEXT: [[Y:%.*]] = insertelement <15 x i8> [[IN:%.*]], i8 64, i32 6
667667
; NOOPT-NEXT: br label [[FINALLY]]
668668
; NOOPT: finally:
669-
; NOOPT-NEXT: [[VAL:%.*]] = phi <15 x i8> [ <i8 poison, i8 1, i8 2, i8 3, i8 4, i8 undef, i8 6, i8 7, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 undef>, [[THEN]] ], [ [[Y]], [[ELSE]] ]
669+
; NOOPT-NEXT: [[VAL:%.*]] = phi <15 x i8> [ <i8 poison, i8 1, i8 2, i8 3, i8 4, i8 poison, i8 6, i8 7, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 poison>, [[THEN]] ], [ [[Y]], [[ELSE]] ]
670670
; NOOPT-NEXT: store <15 x i8> [[VAL]], ptr [[OUT:%.*]], align 1
671671
; NOOPT-NEXT: ret void
672672
;
@@ -678,7 +678,7 @@ else:
678678
%y = insertelement <15 x i8> %in, i8 64, i32 6
679679
br label %finally
680680
finally:
681-
%val = phi <15 x i8> [<i8 poison, i8 1, i8 2, i8 3, i8 4, i8 undef, i8 6, i8 7, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 undef>, %then], [%y, %else]
681+
%val = phi <15 x i8> [<i8 poison, i8 1, i8 2, i8 3, i8 4, i8 poison, i8 6, i8 7, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 poison>, %then], [%y, %else]
682682
store <15 x i8> %val, ptr %out, align 1
683683
ret void
684684
}

‎llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ define amdgpu_hs void @_amdgpu_hs_main(i32 inreg %arg, i32 inreg %arg1, i32 inre
2828
br label %bb
2929

3030
bb: ; preds = %bb, %.endls
31-
%lsr.iv182 = phi ptr addrspace(5) [ undef, %bb ], [ %__llpc_global_proxy_7.i, %.endls ]
31+
%lsr.iv182 = phi ptr addrspace(5) [ poison, %bb ], [ %__llpc_global_proxy_7.i, %.endls ]
3232
%scevgep183 = getelementptr [3 x <4 x float>], ptr addrspace(5) %lsr.iv182, i32 0, i32 1
3333
br label %bb
3434
}

‎llvm/test/CodeGen/AMDGPU/branch-relaxation.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1529,7 +1529,7 @@ bb14: ; preds = %bb13, %bb9
15291529
br label %bb19
15301530

15311531
bb19: ; preds = %bb14, %bb13, %bb9
1532-
%tmp20 = phi i32 [ undef, %bb9 ], [ undef, %bb13 ], [ %tmp18, %bb14 ]
1532+
%tmp20 = phi i32 [ poison, %bb9 ], [ poison, %bb13 ], [ %tmp18, %bb14 ]
15331533
%tmp21 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %arg5
15341534
store i32 %tmp20, ptr addrspace(1) %tmp21, align 4
15351535
ret void

‎llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ define dllexport amdgpu_ps void @_amdgpu_ps_main(i32 %descTable2) #0 {
1818

1919
bb1750: ; preds = %bb1897, %.entry
2020
%__llpc_global_proxy_r3.12.vec.extract2358295 = phi i32 [ 0, %.entry ], [ %__llpc_global_proxy_r3.12.vec.extract2358, %bb1897 ]
21-
%__llpc_global_proxy_r13.20293 = phi <4 x i32> [ undef, %.entry ], [ %__llpc_global_proxy_r13.22, %bb1897 ]
21+
%__llpc_global_proxy_r13.20293 = phi <4 x i32> [ poison, %.entry ], [ %__llpc_global_proxy_r13.22, %bb1897 ]
2222
%__llpc_global_proxy_r10.19291 = phi <4 x i32> [ poison, %.entry ], [ %i1914, %bb1897 ]
2323
%i1751 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %i1746, i32 poison, i32 0, i32 0, i32 0)
2424
%i1754 = shufflevector <4 x i32> %__llpc_global_proxy_r10.19291, <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 7>

‎llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ bb6:
1515
br label %bb8
1616

1717
bb8:
18-
%tmp9 = phi i64 [ %tmp7, %bb6 ], [ undef, %bb2 ]
18+
%tmp9 = phi i64 [ %tmp7, %bb6 ], [ poison, %bb2 ]
1919
%tmp10 = icmp eq i32 %tmp, 0
2020
br i1 %tmp10, label %bb11, label %bb23
2121

@@ -26,16 +26,16 @@ bb17:
2626
br label %bb20
2727

2828
bb20:
29-
%tmp21 = phi i64 [ undef, %bb17 ], [ %tmp9, %bb11 ]
29+
%tmp21 = phi i64 [ poison, %bb17 ], [ %tmp9, %bb11 ]
3030
%tmp22 = trunc i64 %tmp21 to i32
3131
br label %bb23
3232

3333
bb23:
34-
%tmp24 = phi i32 [ %tmp22, %bb20 ], [ undef, %bb8 ], [ undef, %bb ]
34+
%tmp24 = phi i32 [ %tmp22, %bb20 ], [ poison, %bb8 ], [ poison, %bb ]
3535
br label %bb25
3636

3737
bb25:
38-
%tmp26 = phi i32 [ %tmp24, %bb23 ], [ undef, %bb25 ]
38+
%tmp26 = phi i32 [ %tmp24, %bb23 ], [ poison, %bb25 ]
3939
br i1 %c3, label %bb25, label %bb30
4040

4141
bb30:

‎llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,7 @@ bb: ; preds = %.a
7171
br label %bb9
7272

7373
bb9: ; preds = %bb, %.a
74-
%.2.0.in.in = phi i1 [ %i5, %bb ], [ undef, %.a ]
74+
%.2.0.in.in = phi i1 [ %i5, %bb ], [ poison, %.a ]
7575
%.2.0.in = xor i1 %.2.0.in.in, true
7676
%.2.0 = zext i1 %.2.0.in to i32
7777
%i11 = add i32 %.2, %.2.0
@@ -151,7 +151,7 @@ bb: ; preds = %.a
151151
br label %bb9
152152

153153
bb9: ; preds = %bb, %.a
154-
%.2.0.in.in = phi i1 [ %i5, %bb ], [ undef, %.a ]
154+
%.2.0.in.in = phi i1 [ %i5, %bb ], [ poison, %.a ]
155155
%.2.0.in = xor i1 %.2.0.in.in, true
156156
%.2.0 = zext i1 %.2.0.in to i32
157157
%i11 = sub i32 %.2, %.2.0
@@ -234,7 +234,7 @@ bb: ; preds = %.a
234234
br label %bb9
235235

236236
bb9: ; preds = %bb, %.a
237-
%.2.0.in.in = phi i1 [ %i5, %bb ], [ undef, %.a ]
237+
%.2.0.in.in = phi i1 [ %i5, %bb ], [ poison, %.a ]
238238
%t = icmp sgt i32 %.2, -1050
239239
%.2.0.in = or i1 %.2.0.in.in, %t
240240
%.2.0 = zext i1 %.2.0.in to i32
@@ -318,7 +318,7 @@ bb: ; preds = %.a
318318
br label %bb9
319319

320320
bb9: ; preds = %bb, %.a
321-
%.2.0.in.in = phi i1 [ %i5, %bb ], [ undef, %.a ]
321+
%.2.0.in.in = phi i1 [ %i5, %bb ], [ poison, %.a ]
322322
%t = icmp sgt i32 %.2, -1050
323323
%.2.0.in = or i1 %.2.0.in.in, %t
324324
%.2.0 = zext i1 %.2.0.in to i32
@@ -397,7 +397,7 @@ bb: ; preds = %.a
397397
br label %bb9
398398

399399
bb9: ; preds = %bb, %.a
400-
%.2.0.in.in = phi i1 [ %i5, %bb ], [ undef, %.a ]
400+
%.2.0.in.in = phi i1 [ %i5, %bb ], [ poison, %.a ]
401401
%t = icmp sgt i32 %.2, -1050
402402
%.2.0.in = and i1 %.2.0.in.in, %t
403403
%.2.0 = zext i1 %.2.0.in to i32
@@ -476,7 +476,7 @@ bb: ; preds = %.a
476476
br label %bb9
477477

478478
bb9: ; preds = %bb, %.a
479-
%.2.0.in.in = phi i1 [ %i5, %bb ], [ undef, %.a ]
479+
%.2.0.in.in = phi i1 [ %i5, %bb ], [ poison, %.a ]
480480
%t = icmp sgt i32 %.2, -1050
481481
%.2.0.in = and i1 %.2.0.in.in, %t
482482
%.2.0 = zext i1 %.2.0.in to i32

‎llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ bb9: ; preds = %bb5
3030
br label %bb10
3131

3232
bb10: ; preds = %bb9, %bb5, %bb3, %bb
33-
%tmp11 = phi float [ 1.000000e+00, %bb3 ], [ 0.000000e+00, %bb9 ], [ 1.000000e+00, %bb ], [ undef, %bb5 ]
33+
%tmp11 = phi float [ 1.000000e+00, %bb3 ], [ 0.000000e+00, %bb9 ], [ 1.000000e+00, %bb ], [ poison, %bb5 ]
3434
call void @llvm.amdgcn.exp.f32(i32 40, i32 15, float %tmp11, float undef, float undef, float undef, i1 false, i1 false) #0
3535
ret void
3636
}

‎llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ bb:
2525
br label %bb12
2626

2727
bb12:
28-
%__llpc_global_proxy_r2.0 = phi <4 x i32> [ %__llpc_global_proxy_r2.0.vec.insert196, %bb ], [ undef, %.entry ]
28+
%__llpc_global_proxy_r2.0 = phi <4 x i32> [ %__llpc_global_proxy_r2.0.vec.insert196, %bb ], [ poison, %.entry ]
2929
%tmp6 = shufflevector <4 x i32> %__llpc_global_proxy_r2.0, <4 x i32> undef, <3 x i32> <i32 1, i32 2, i32 3>
3030
%tmp7 = bitcast <3 x i32> %tmp6 to <3 x float>
3131
%a0.i = extractelement <3 x float> %tmp7, i32 0

‎llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -64,8 +64,8 @@ bb2:
6464
br label %bb11
6565

6666
bb11:
67-
%i12 = phi float [ %i6, %bb2 ], [ undef, %bb ]
68-
%i13 = phi float [ %i10, %bb2 ], [ undef, %bb ]
67+
%i12 = phi float [ %i6, %bb2 ], [ poison, %bb ]
68+
%i13 = phi float [ %i10, %bb2 ], [ poison, %bb ]
6969
%i14 = phi i1 [ false, %bb2 ], [ true, %bb ]
7070
br i1 %i14, label %bb15, label %bb17
7171

‎llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ loop: ; preds = %Flow, %start
7878
br i1 %2, label %endif1, label %Flow
7979

8080
Flow1: ; preds = %endif2, %endif1
81-
%3 = phi i32 [ %v5, %endif2 ], [ undef, %endif1 ]
81+
%3 = phi i32 [ %v5, %endif2 ], [ poison, %endif1 ]
8282
%4 = phi i1 [ false, %endif2 ], [ true, %endif1 ]
8383
br label %Flow
8484

@@ -107,7 +107,7 @@ endif1: ; preds = %loop
107107
br i1 %5, label %endif2, label %Flow1
108108

109109
Flow: ; preds = %Flow1, %loop
110-
%6 = phi i32 [ %3, %Flow1 ], [ undef, %loop ]
110+
%6 = phi i32 [ %3, %Flow1 ], [ poison, %loop ]
111111
%7 = phi i1 [ %4, %Flow1 ], [ true, %loop ]
112112
%8 = phi i1 [ false, %Flow1 ], [ true, %loop ]
113113
br i1 %7, label %Flow2, label %loop

‎llvm/test/CodeGen/AMDGPU/fold-fabs.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -179,7 +179,7 @@ entry:
179179
br i1 %4, label %header, label %exit
180180

181181
header:
182-
%h.fabs.phi = phi float [ undef, %entry ], [ %l.fabs, %l ]
182+
%h.fabs.phi = phi float [ poison, %entry ], [ %l.fabs, %l ]
183183
%h.fmul = fmul reassoc nnan nsz arcp contract afn float %h.fabs.phi, 2.000000e+00
184184
%l.1 = fmul reassoc nnan nsz arcp contract afn float %h.fabs.phi, 3.000000e+00
185185
br label %l

‎llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@ false:
5252
br label %exit
5353

5454
exit:
55-
%c = phi <2 x i1> [ undef, %entry ], [ %cmp, %false ]
55+
%c = phi <2 x i1> [ poison, %entry ], [ %cmp, %false ]
5656
%ret = select <2 x i1> %c, <2 x float> <float 2.0, float 2.0>, <2 x float> <float 4.0, float 4.0>
5757
ret <2 x float> %ret
5858
}

‎llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ false:
1818
br label %exit
1919

2020
exit:
21-
%c = phi <2 x i1> [ undef, %entry ], [ %cmp, %false ]
21+
%c = phi <2 x i1> [ poison, %entry ], [ %cmp, %false ]
2222
%ret = select <2 x i1> %c, <2 x float> <float 2.0, float 2.0>, <2 x float> <float 4.0, float 4.0>
2323
ret <2 x float> %ret
2424
}

‎llvm/test/CodeGen/AMDGPU/inline-asm.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -307,7 +307,7 @@ false:
307307
br label %exit
308308

309309
exit:
310-
%s1 = phi { i64, i64} [ undef, %entry ], [ %s0, %false]
310+
%s1 = phi { i64, i64} [ poison, %entry ], [ %s0, %false]
311311
%v0 = extractvalue { i64, i64 } %s1, 0
312312
%v1 = extractvalue { i64, i64 } %s1, 1
313313
tail call void asm sideeffect "; use $0", "v"(i64 %v0)

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ if-true:
4141
br label %endif
4242

4343
endif:
44-
%v = phi i32 [ %val, %if-true ], [ undef, %entry ]
44+
%v = phi i32 [ %val, %if-true ], [ poison, %entry ]
4545
%r = bitcast i32 %v to float
4646
ret float %r
4747
}

‎llvm/test/CodeGen/AMDGPU/madmk.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -199,7 +199,7 @@ bb1: ; preds = %bb2
199199
ret void
200200

201201
bb2: ; preds = %bb6, %bb
202-
%tmp = phi float [ undef, %bb ], [ %tmp8, %bb6 ]
202+
%tmp = phi float [ poison, %bb ], [ %tmp8, %bb6 ]
203203
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #1
204204
%f_tid = bitcast i32 %tid to float
205205
%tmp3 = fsub float %f_tid, %tmp

‎llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ if.then3.i: ; preds = %if.end60
4848
br label %if.end5.i
4949

5050
if.end5.i: ; preds = %if.then3.i, %if.end60
51-
%pS.addr.0.i = phi ptr addrspace(5) [ undef, %if.then3.i ], [ %runtimeVersionCopy, %if.end60 ]
51+
%pS.addr.0.i = phi ptr addrspace(5) [ poison, %if.then3.i ], [ %runtimeVersionCopy, %if.end60 ]
5252
%2 = load i8, ptr addrspace(5) %pS.addr.0.i, align 1
5353
%conv612.i = sext i8 %2 to i32
5454
%sub13.i = add nsw i32 %conv612.i, -48
@@ -65,7 +65,7 @@ if.then3.i308: ; preds = %if.end5.i
6565
br label %if.end5.i314
6666

6767
if.end5.i314: ; preds = %if.then3.i308, %if.end5.i
68-
%pS.addr.0.i309 = phi ptr addrspace(5) [ undef, %if.then3.i308 ], [ %licenseVersionCopy, %if.end5.i ]
68+
%pS.addr.0.i309 = phi ptr addrspace(5) [ poison, %if.then3.i308 ], [ %licenseVersionCopy, %if.end5.i ]
6969
%3 = load i8, ptr addrspace(5) %pS.addr.0.i309, align 1
7070
%conv612.i311 = sext i8 %3 to i32
7171
%sub13.i312 = add nsw i32 %conv612.i311, -48
@@ -82,7 +82,7 @@ if.then3.i332: ; preds = %if.end5.i314
8282
br label %if.end5.i338
8383

8484
if.end5.i338: ; preds = %if.then3.i332, %if.end5.i314
85-
%pS.addr.0.i333 = phi ptr addrspace(5) [ undef, %if.then3.i332 ], [ %arrayidx144260.5, %if.end5.i314 ]
85+
%pS.addr.0.i333 = phi ptr addrspace(5) [ poison, %if.then3.i332 ], [ %arrayidx144260.5, %if.end5.i314 ]
8686
%4 = load i8, ptr addrspace(5) %pS.addr.0.i333, align 1
8787
%conv612.i335 = sext i8 %4 to i32
8888
%sub13.i336 = add nsw i32 %conv612.i335, -48
@@ -99,7 +99,7 @@ if.then3.i356: ; preds = %if.end5.i338
9999
br label %if.end5.i362
100100

101101
if.end5.i362: ; preds = %if.then3.i356, %if.end5.i338
102-
%pS.addr.0.i357 = phi ptr addrspace(5) [ undef, %if.then3.i356 ], [ %arrayidx156258.5, %if.end5.i338 ]
102+
%pS.addr.0.i357 = phi ptr addrspace(5) [ poison, %if.then3.i356 ], [ %arrayidx156258.5, %if.end5.i338 ]
103103
%5 = load i8, ptr addrspace(5) %pS.addr.0.i357, align 1
104104
%conv612.i359 = sext i8 %5 to i32
105105
%sub13.i360 = add nsw i32 %conv612.i359, -48
@@ -120,7 +120,7 @@ if.then3.i394: ; preds = %if.end5.i362
120120
br label %if.end5.i400
121121

122122
if.end5.i400: ; preds = %if.then3.i394, %if.end5.i362
123-
%pS.addr.0.i395 = phi ptr addrspace(5) [ %arrayidx232250.1, %if.then3.i394 ], [ undef, %if.end5.i362 ]
123+
%pS.addr.0.i395 = phi ptr addrspace(5) [ %arrayidx232250.1, %if.then3.i394 ], [ poison, %if.end5.i362 ]
124124
%7 = load i8, ptr addrspace(5) %pS.addr.0.i395, align 1
125125
%conv612.i397 = sext i8 %7 to i32
126126
%sub13.i398 = add nsw i32 %conv612.i397, -48

‎llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,8 @@ bb:
1717
br label %bb1
1818

1919
bb1: ; preds = %bb1, %bb
20-
%tmp2 = phi i64 [ undef, %bb ], [ %tmp16, %bb1 ]
21-
%tmp3 = phi i64 [ %tmp, %bb ], [ undef, %bb1 ]
20+
%tmp2 = phi i64 [ poison, %bb ], [ %tmp16, %bb1 ]
21+
%tmp3 = phi i64 [ %tmp, %bb ], [ poison, %bb1 ]
2222
%tmp11 = shl i64 %tmp2, 14
2323
%tmp13 = xor i64 %tmp11, %tmp2
2424
%tmp15 = and i64 %tmp3, %tmp13

‎llvm/test/CodeGen/AMDGPU/multilevel-break.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -120,7 +120,7 @@ define amdgpu_kernel void @multi_if_break_loop(i32 %arg) #0 {
120120
; OPT-NEXT: br label [[BB1:%.*]]
121121
; OPT: bb1:
122122
; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP4:%.*]], [[FLOW4:%.*]] ], [ 0, [[BB:%.*]] ]
123-
; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[TMP2:%.*]], [[FLOW4]] ]
123+
; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ poison, [[BB]] ], [ [[TMP2:%.*]], [[FLOW4]] ]
124124
; OPT-NEXT: [[LSR_IV_NEXT:%.*]] = add i32 [[LSR_IV]], 1
125125
; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
126126
; OPT-NEXT: [[LOAD0:%.*]] = load volatile i32, ptr addrspace(1) undef, align 4
@@ -227,7 +227,7 @@ bb:
227227
br label %bb1
228228

229229
bb1:
230-
%lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %case0 ], [ %lsr.iv.next, %case1 ]
230+
%lsr.iv = phi i32 [ poison, %bb ], [ %lsr.iv.next, %case0 ], [ %lsr.iv.next, %case1 ]
231231
%lsr.iv.next = add i32 %lsr.iv, 1
232232
%cmp0 = icmp slt i32 %lsr.iv.next, 0
233233
%load0 = load volatile i32, ptr addrspace(1) undef, align 4

‎llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ define amdgpu_kernel void @reduced_nested_loop_conditions(ptr addrspace(3) captu
7474
; IR-NEXT: br i1 [[TMP3]], label %[[BB23:.*]], label %[[BB5]]
7575
; IR: [[FLOW]]:
7676
; IR-NEXT: [[TMP4:%.*]] = phi i1 [ [[MY_TMP22:%.*]], %[[BB4]] ], [ true, %[[BB5]] ]
77-
; IR-NEXT: [[TMP5]] = phi i32 [ [[MY_TMP21:%.*]], %[[BB4]] ], [ undef, %[[BB5]] ]
77+
; IR-NEXT: [[TMP5]] = phi i32 [ [[MY_TMP21:%.*]], %[[BB4]] ], [ poison, %[[BB5]] ]
7878
; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP2]])
7979
; IR-NEXT: [[TMP6]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP4]], i64 [[PHI_BROKEN]])
8080
; IR-NEXT: br label %[[BB10]]
@@ -118,7 +118,7 @@ bb9: ; preds = %bb20, %bb9
118118
br i1 false, label %bb3, label %bb9
119119

120120
bb10: ; preds = %bb5, %bb4
121-
%my.tmp11 = phi i32 [ %my.tmp21, %bb4 ], [ undef, %bb5 ]
121+
%my.tmp11 = phi i32 [ %my.tmp21, %bb4 ], [ poison, %bb5 ]
122122
%my.tmp12 = phi i1 [ %my.tmp22, %bb4 ], [ true, %bb5 ]
123123
br i1 %my.tmp12, label %bb23, label %bb5
124124

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