AMDGPU: Replace undef phi inputs with poison in tests #130267
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@llvm/pr-subscribers-llvm-globalisel @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) ChangesI think the chance of this changing the tests in meaningful ways Patch is 41.99 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/130267.diff 35 Files Affected:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
index e7ddfda2875db..cc768a2cdf61f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
@@ -26,7 +26,7 @@ if.true:
br label %endif
endif:
- %v = phi i32 [ %val, %if.true ], [ undef, %entry ]
+ %v = phi i32 [ %val, %if.true ], [ poison, %entry ]
ret i32 %v
}
@@ -49,7 +49,7 @@ entry:
br i1 %c, label %if.true, label %endif
endif:
- %v = phi i32 [ %val, %if.true ], [ undef, %entry ]
+ %v = phi i32 [ %val, %if.true ], [ poison, %entry ]
ret i32 %v
if.true:
@@ -82,7 +82,7 @@ if.true:
br label %endif
endif:
- %v = phi i32 [ %val, %if.true ], [ undef, %entry ]
+ %v = phi i32 [ %val, %if.true ], [ poison, %entry ]
ret i32 %v
}
@@ -114,7 +114,7 @@ if.true:
br label %endif
endif:
- %v = phi i32 [ %val, %if.true ], [ undef, %entry ]
+ %v = phi i32 [ %val, %if.true ], [ poison, %entry ]
ret i32 %v
}
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-break-large-phis.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-break-large-phis.ll
index 11772d252a16f..dc2a6137dba3b 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-break-large-phis.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-break-large-phis.ll
@@ -643,11 +643,11 @@ define amdgpu_kernel void @phi_v15i8_random_constant_init(<15 x i8> %in, ptr %ou
; OPT-NEXT: br label [[FINALLY]]
; OPT: finally:
; OPT-NEXT: [[TMP0:%.*]] = phi <4 x i8> [ <i8 poison, i8 1, i8 2, i8 3>, [[THEN]] ], [ [[LARGEPHI_EXTRACTSLICE1]], [[ELSE]] ]
-; OPT-NEXT: [[TMP1:%.*]] = phi <4 x i8> [ <i8 4, i8 undef, i8 6, i8 7>, [[THEN]] ], [ [[LARGEPHI_EXTRACTSLICE3]], [[ELSE]] ]
+; OPT-NEXT: [[TMP1:%.*]] = phi <4 x i8> [ <i8 4, i8 poison, i8 6, i8 7>, [[THEN]] ], [ [[LARGEPHI_EXTRACTSLICE3]], [[ELSE]] ]
; OPT-NEXT: [[TMP2:%.*]] = phi <4 x i8> [ <i8 9, i8 10, i8 11, i8 12>, [[THEN]] ], [ [[LARGEPHI_EXTRACTSLICE5]], [[ELSE]] ]
; OPT-NEXT: [[TMP3:%.*]] = phi i8 [ 13, [[THEN]] ], [ [[LARGEPHI_EXTRACTSLICE7]], [[ELSE]] ]
; OPT-NEXT: [[TMP4:%.*]] = phi i8 [ 14, [[THEN]] ], [ [[LARGEPHI_EXTRACTSLICE9]], [[ELSE]] ]
-; OPT-NEXT: [[TMP5:%.*]] = phi i8 [ undef, [[THEN]] ], [ [[LARGEPHI_EXTRACTSLICE11]], [[ELSE]] ]
+; OPT-NEXT: [[TMP5:%.*]] = phi i8 [ poison, [[THEN]] ], [ [[LARGEPHI_EXTRACTSLICE11]], [[ELSE]] ]
; OPT-NEXT: [[LARGEPHI_INSERTSLICE0:%.*]] = call <15 x i8> @llvm.vector.insert.v15i8.v4i8(<15 x i8> poison, <4 x i8> [[TMP0]], i64 0)
; OPT-NEXT: [[LARGEPHI_INSERTSLICE1:%.*]] = call <15 x i8> @llvm.vector.insert.v15i8.v4i8(<15 x i8> [[LARGEPHI_INSERTSLICE0]], <4 x i8> [[TMP1]], i64 4)
; OPT-NEXT: [[LARGEPHI_INSERTSLICE2:%.*]] = call <15 x i8> @llvm.vector.insert.v15i8.v4i8(<15 x i8> [[LARGEPHI_INSERTSLICE1]], <4 x i8> [[TMP2]], i64 8)
@@ -666,7 +666,7 @@ define amdgpu_kernel void @phi_v15i8_random_constant_init(<15 x i8> %in, ptr %ou
; NOOPT-NEXT: [[Y:%.*]] = insertelement <15 x i8> [[IN:%.*]], i8 64, i32 6
; NOOPT-NEXT: br label [[FINALLY]]
; NOOPT: finally:
-; NOOPT-NEXT: [[VAL:%.*]] = phi <15 x i8> [ <i8 poison, i8 1, i8 2, i8 3, i8 4, i8 undef, i8 6, i8 7, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 undef>, [[THEN]] ], [ [[Y]], [[ELSE]] ]
+; NOOPT-NEXT: [[VAL:%.*]] = phi <15 x i8> [ <i8 poison, i8 1, i8 2, i8 3, i8 4, i8 poison, i8 6, i8 7, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 poison>, [[THEN]] ], [ [[Y]], [[ELSE]] ]
; NOOPT-NEXT: store <15 x i8> [[VAL]], ptr [[OUT:%.*]], align 1
; NOOPT-NEXT: ret void
;
@@ -678,7 +678,7 @@ else:
%y = insertelement <15 x i8> %in, i8 64, i32 6
br label %finally
finally:
- %val = phi <15 x i8> [<i8 poison, i8 1, i8 2, i8 3, i8 4, i8 undef, i8 6, i8 7, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 undef>, %then], [%y, %else]
+ %val = phi <15 x i8> [<i8 poison, i8 1, i8 2, i8 3, i8 4, i8 poison, i8 6, i8 7, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 poison>, %then], [%y, %else]
store <15 x i8> %val, ptr %out, align 1
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll b/llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
index 20e1d6abc7978..2aea4497c12ba 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
@@ -28,7 +28,7 @@ define amdgpu_hs void @_amdgpu_hs_main(i32 inreg %arg, i32 inreg %arg1, i32 inre
br label %bb
bb: ; preds = %bb, %.endls
- %lsr.iv182 = phi ptr addrspace(5) [ undef, %bb ], [ %__llpc_global_proxy_7.i, %.endls ]
+ %lsr.iv182 = phi ptr addrspace(5) [ poison, %bb ], [ %__llpc_global_proxy_7.i, %.endls ]
%scevgep183 = getelementptr [3 x <4 x float>], ptr addrspace(5) %lsr.iv182, i32 0, i32 1
br label %bb
}
diff --git a/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll b/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
index a03ad4daab014..2cd15210eb8e5 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
+++ b/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
@@ -1529,7 +1529,7 @@ bb14: ; preds = %bb13, %bb9
br label %bb19
bb19: ; preds = %bb14, %bb13, %bb9
- %tmp20 = phi i32 [ undef, %bb9 ], [ undef, %bb13 ], [ %tmp18, %bb14 ]
+ %tmp20 = phi i32 [ poison, %bb9 ], [ poison, %bb13 ], [ %tmp18, %bb14 ]
%tmp21 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %arg5
store i32 %tmp20, ptr addrspace(1) %tmp21, align 4
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll b/llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll
index 98590c227859b..831017fae3111 100644
--- a/llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll
+++ b/llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll
@@ -18,7 +18,7 @@ define dllexport amdgpu_ps void @_amdgpu_ps_main(i32 %descTable2) #0 {
bb1750: ; preds = %bb1897, %.entry
%__llpc_global_proxy_r3.12.vec.extract2358295 = phi i32 [ 0, %.entry ], [ %__llpc_global_proxy_r3.12.vec.extract2358, %bb1897 ]
- %__llpc_global_proxy_r13.20293 = phi <4 x i32> [ undef, %.entry ], [ %__llpc_global_proxy_r13.22, %bb1897 ]
+ %__llpc_global_proxy_r13.20293 = phi <4 x i32> [ poison, %.entry ], [ %__llpc_global_proxy_r13.22, %bb1897 ]
%__llpc_global_proxy_r10.19291 = phi <4 x i32> [ poison, %.entry ], [ %i1914, %bb1897 ]
%i1751 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %i1746, i32 poison, i32 0, i32 0, i32 0)
%i1754 = shufflevector <4 x i32> %__llpc_global_proxy_r10.19291, <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll b/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll
index 2d8ef336f52d6..8f4d10411ed73 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll
+++ b/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll
@@ -15,7 +15,7 @@ bb6:
br label %bb8
bb8:
- %tmp9 = phi i64 [ %tmp7, %bb6 ], [ undef, %bb2 ]
+ %tmp9 = phi i64 [ %tmp7, %bb6 ], [ poison, %bb2 ]
%tmp10 = icmp eq i32 %tmp, 0
br i1 %tmp10, label %bb11, label %bb23
@@ -26,16 +26,16 @@ bb17:
br label %bb20
bb20:
- %tmp21 = phi i64 [ undef, %bb17 ], [ %tmp9, %bb11 ]
+ %tmp21 = phi i64 [ poison, %bb17 ], [ %tmp9, %bb11 ]
%tmp22 = trunc i64 %tmp21 to i32
br label %bb23
bb23:
- %tmp24 = phi i32 [ %tmp22, %bb20 ], [ undef, %bb8 ], [ undef, %bb ]
+ %tmp24 = phi i32 [ %tmp22, %bb20 ], [ poison, %bb8 ], [ poison, %bb ]
br label %bb25
bb25:
- %tmp26 = phi i32 [ %tmp24, %bb23 ], [ undef, %bb25 ]
+ %tmp26 = phi i32 [ %tmp24, %bb23 ], [ poison, %bb25 ]
br i1 %c3, label %bb25, label %bb30
bb30:
diff --git a/llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll b/llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
index a25078230385e..b42542db6dbd8 100644
--- a/llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
+++ b/llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
@@ -71,7 +71,7 @@ bb: ; preds = %.a
br label %bb9
bb9: ; preds = %bb, %.a
- %.2.0.in.in = phi i1 [ %i5, %bb ], [ undef, %.a ]
+ %.2.0.in.in = phi i1 [ %i5, %bb ], [ poison, %.a ]
%.2.0.in = xor i1 %.2.0.in.in, true
%.2.0 = zext i1 %.2.0.in to i32
%i11 = add i32 %.2, %.2.0
@@ -151,7 +151,7 @@ bb: ; preds = %.a
br label %bb9
bb9: ; preds = %bb, %.a
- %.2.0.in.in = phi i1 [ %i5, %bb ], [ undef, %.a ]
+ %.2.0.in.in = phi i1 [ %i5, %bb ], [ poison, %.a ]
%.2.0.in = xor i1 %.2.0.in.in, true
%.2.0 = zext i1 %.2.0.in to i32
%i11 = sub i32 %.2, %.2.0
@@ -234,7 +234,7 @@ bb: ; preds = %.a
br label %bb9
bb9: ; preds = %bb, %.a
- %.2.0.in.in = phi i1 [ %i5, %bb ], [ undef, %.a ]
+ %.2.0.in.in = phi i1 [ %i5, %bb ], [ poison, %.a ]
%t = icmp sgt i32 %.2, -1050
%.2.0.in = or i1 %.2.0.in.in, %t
%.2.0 = zext i1 %.2.0.in to i32
@@ -318,7 +318,7 @@ bb: ; preds = %.a
br label %bb9
bb9: ; preds = %bb, %.a
- %.2.0.in.in = phi i1 [ %i5, %bb ], [ undef, %.a ]
+ %.2.0.in.in = phi i1 [ %i5, %bb ], [ poison, %.a ]
%t = icmp sgt i32 %.2, -1050
%.2.0.in = or i1 %.2.0.in.in, %t
%.2.0 = zext i1 %.2.0.in to i32
@@ -397,7 +397,7 @@ bb: ; preds = %.a
br label %bb9
bb9: ; preds = %bb, %.a
- %.2.0.in.in = phi i1 [ %i5, %bb ], [ undef, %.a ]
+ %.2.0.in.in = phi i1 [ %i5, %bb ], [ poison, %.a ]
%t = icmp sgt i32 %.2, -1050
%.2.0.in = and i1 %.2.0.in.in, %t
%.2.0 = zext i1 %.2.0.in to i32
@@ -476,7 +476,7 @@ bb: ; preds = %.a
br label %bb9
bb9: ; preds = %bb, %.a
- %.2.0.in.in = phi i1 [ %i5, %bb ], [ undef, %.a ]
+ %.2.0.in.in = phi i1 [ %i5, %bb ], [ poison, %.a ]
%t = icmp sgt i32 %.2, -1050
%.2.0.in = and i1 %.2.0.in.in, %t
%.2.0 = zext i1 %.2.0.in to i32
diff --git a/llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll b/llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll
index 4f0d040e3217c..c73a3b69d3716 100644
--- a/llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll
+++ b/llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll
@@ -30,7 +30,7 @@ bb9: ; preds = %bb5
br label %bb10
bb10: ; preds = %bb9, %bb5, %bb3, %bb
- %tmp11 = phi float [ 1.000000e+00, %bb3 ], [ 0.000000e+00, %bb9 ], [ 1.000000e+00, %bb ], [ undef, %bb5 ]
+ %tmp11 = phi float [ 1.000000e+00, %bb3 ], [ 0.000000e+00, %bb9 ], [ 1.000000e+00, %bb ], [ poison, %bb5 ]
call void @llvm.amdgcn.exp.f32(i32 40, i32 15, float %tmp11, float undef, float undef, float undef, i1 false, i1 false) #0
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll b/llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll
index 009590ed9e410..7d14a5b811b7f 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll
@@ -25,7 +25,7 @@ bb:
br label %bb12
bb12:
- %__llpc_global_proxy_r2.0 = phi <4 x i32> [ %__llpc_global_proxy_r2.0.vec.insert196, %bb ], [ undef, %.entry ]
+ %__llpc_global_proxy_r2.0 = phi <4 x i32> [ %__llpc_global_proxy_r2.0.vec.insert196, %bb ], [ poison, %.entry ]
%tmp6 = shufflevector <4 x i32> %__llpc_global_proxy_r2.0, <4 x i32> undef, <3 x i32> <i32 1, i32 2, i32 3>
%tmp7 = bitcast <3 x i32> %tmp6 to <3 x float>
%a0.i = extractelement <3 x float> %tmp7, i32 0
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
index 29e4bd55c4b90..142494a803755 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
@@ -64,8 +64,8 @@ bb2:
br label %bb11
bb11:
- %i12 = phi float [ %i6, %bb2 ], [ undef, %bb ]
- %i13 = phi float [ %i10, %bb2 ], [ undef, %bb ]
+ %i12 = phi float [ %i6, %bb2 ], [ poison, %bb ]
+ %i13 = phi float [ %i10, %bb2 ], [ poison, %bb ]
%i14 = phi i1 [ false, %bb2 ], [ true, %bb ]
br i1 %i14, label %bb15, label %bb17
diff --git a/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll b/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
index db7897d70fa93..827cb4ac2589a 100644
--- a/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
@@ -78,7 +78,7 @@ loop: ; preds = %Flow, %start
br i1 %2, label %endif1, label %Flow
Flow1: ; preds = %endif2, %endif1
- %3 = phi i32 [ %v5, %endif2 ], [ undef, %endif1 ]
+ %3 = phi i32 [ %v5, %endif2 ], [ poison, %endif1 ]
%4 = phi i1 [ false, %endif2 ], [ true, %endif1 ]
br label %Flow
@@ -107,7 +107,7 @@ endif1: ; preds = %loop
br i1 %5, label %endif2, label %Flow1
Flow: ; preds = %Flow1, %loop
- %6 = phi i32 [ %3, %Flow1 ], [ undef, %loop ]
+ %6 = phi i32 [ %3, %Flow1 ], [ poison, %loop ]
%7 = phi i1 [ %4, %Flow1 ], [ true, %loop ]
%8 = phi i1 [ false, %Flow1 ], [ true, %loop ]
br i1 %7, label %Flow2, label %loop
diff --git a/llvm/test/CodeGen/AMDGPU/fold-fabs.ll b/llvm/test/CodeGen/AMDGPU/fold-fabs.ll
index a04bf44549325..6a8594a168f03 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-fabs.ll
+++ b/llvm/test/CodeGen/AMDGPU/fold-fabs.ll
@@ -179,7 +179,7 @@ entry:
br i1 %4, label %header, label %exit
header:
- %h.fabs.phi = phi float [ undef, %entry ], [ %l.fabs, %l ]
+ %h.fabs.phi = phi float [ poison, %entry ], [ %l.fabs, %l ]
%h.fmul = fmul reassoc nnan nsz arcp contract afn float %h.fabs.phi, 2.000000e+00
%l.1 = fmul reassoc nnan nsz arcp contract afn float %h.fabs.phi, 3.000000e+00
br label %l
diff --git a/llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll b/llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll
index 80aa6ee0ab103..2c062bbd81867 100644
--- a/llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll
+++ b/llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll
@@ -52,7 +52,7 @@ false:
br label %exit
exit:
- %c = phi <2 x i1> [ undef, %entry ], [ %cmp, %false ]
+ %c = phi <2 x i1> [ poison, %entry ], [ %cmp, %false ]
%ret = select <2 x i1> %c, <2 x float> <float 2.0, float 2.0>, <2 x float> <float 4.0, float 4.0>
ret <2 x float> %ret
}
diff --git a/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll b/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
index aabe4e930f708..495e8a281b05b 100644
--- a/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
+++ b/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
@@ -18,7 +18,7 @@ false:
br label %exit
exit:
- %c = phi <2 x i1> [ undef, %entry ], [ %cmp, %false ]
+ %c = phi <2 x i1> [ poison, %entry ], [ %cmp, %false ]
%ret = select <2 x i1> %c, <2 x float> <float 2.0, float 2.0>, <2 x float> <float 4.0, float 4.0>
ret <2 x float> %ret
}
diff --git a/llvm/test/CodeGen/AMDGPU/inline-asm.ll b/llvm/test/CodeGen/AMDGPU/inline-asm.ll
index 881433f48c76f..4a6dd870fe62d 100644
--- a/llvm/test/CodeGen/AMDGPU/inline-asm.ll
+++ b/llvm/test/CodeGen/AMDGPU/inline-asm.ll
@@ -307,7 +307,7 @@ false:
br label %exit
exit:
- %s1 = phi { i64, i64} [ undef, %entry ], [ %s0, %false]
+ %s1 = phi { i64, i64} [ poison, %entry ], [ %s0, %false]
%v0 = extractvalue { i64, i64 } %s1, 0
%v1 = extractvalue { i64, i64 } %s1, 1
tail call void asm sideeffect "; use $0", "v"(i64 %v0)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll
index cee5bbbe85f48..c9f089e248e76 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll
@@ -41,7 +41,7 @@ if-true:
br label %endif
endif:
- %v = phi i32 [ %val, %if-true ], [ undef, %entry ]
+ %v = phi i32 [ %val, %if-true ], [ poison, %entry ]
%r = bitcast i32 %v to float
ret float %r
}
diff --git a/llvm/test/CodeGen/AMDGPU/madmk.ll b/llvm/test/CodeGen/AMDGPU/madmk.ll
index d5ef866dc8a85..1769b7418b232 100644
--- a/llvm/test/CodeGen/AMDGPU/madmk.ll
+++ b/llvm/test/CodeGen/AMDGPU/madmk.ll
@@ -199,7 +199,7 @@ bb1: ; preds = %bb2
ret void
bb2: ; preds = %bb6, %bb
- %tmp = phi float [ undef, %bb ], [ %tmp8, %bb6 ]
+ %tmp = phi float [ poison, %bb ], [ %tmp8, %bb6 ]
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #1
%f_tid = bitcast i32 %tid to float
%tmp3 = fsub float %f_tid, %tmp
diff --git a/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll b/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
index 1d0533ca07b3e..6d4467a541203 100644
--- a/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
@@ -48,7 +48,7 @@ if.then3.i: ; preds = %if.end60
br label %if.end5.i
if.end5.i: ; preds = %if.then3.i, %if.end60
- %pS.addr.0.i = phi ptr addrspace(5) [ undef, %if.then3.i ], [ %runtimeVersionCopy, %if.end60 ]
+ %pS.addr.0.i = phi ptr addrspace(5) [ poison, %if.then3.i ], [ %runtimeVersionCopy, %if.end60 ]
%2 = load i8, ptr addrspace(5) %pS.addr.0.i, align 1
%conv612.i = sext i8 %2 to i32
%sub13.i = add nsw i32 %conv612.i, -48
@@ -65,7 +65,7 @@ if.then3.i308: ; preds = %if.end5.i
br label %if.end5.i314
if.end5.i314: ; preds = %if.then3.i308, %if.end5.i
- %pS.addr.0.i309 = phi ptr addrspace(5) [ undef, %if.then3.i308 ], [ %licenseVersionCopy, %if.end5.i ]
+ %pS.addr.0.i309 = phi ptr addrspace(5) [ poison, %if.then3.i308 ], [ %licenseVersionCopy, %if.end5.i ]
%3 = load i8, ptr addrspace(5) %pS.addr.0.i309, align 1
%conv612.i311 = sext i8 %3 to i32
%sub13.i312 = add nsw i32 %conv612.i311, -48
@@ -82,7 +82,7 @@ if.then3.i332: ; preds = %if.end5.i314
br label %if.end5.i338
if.end5.i338: ; preds = %if.then3.i332, %if.end5.i314
- %pS.addr.0.i333 = phi ptr addrspace(5) [ undef, %if.then3.i332 ], [ %arrayidx144260.5, %if.end5.i314 ]
+ %pS.addr.0.i333 = phi ptr addrspace(5) [ poison, %if.then3.i332 ], [ %arrayidx144260.5, %if.end5.i314 ]
%4 = load i8, ptr addrspace(5) %pS.addr.0.i333, align 1
%conv612.i335 = sext i8 %4 to i32
%sub13.i336 = add nsw i32 %conv612.i335, -48
@@ -99,7 +99,7 @@ if.then3.i356: ; preds = %if.end5.i338
br label %if.end5.i362
if.end5.i362: ; preds = %if.then3.i356, %if.end5.i338
- %pS.addr.0.i357 = phi ptr addrspace(5) [ undef, %if.then3.i356 ], [ %arrayidx156258.5, %if.end5.i338 ]
+ %pS.addr.0.i357 = phi ptr addrspace(5) [ poison, %if.then3.i356 ], [ %arrayidx156258.5, %if.end5.i338 ]
%5 = load i8, ptr addrspace(5) %pS.addr.0.i357, align 1
%conv612.i359 = sext i8 %5 to i32
%sub13.i360 = add nsw i32 %conv612.i359, -48
@@ -120,7 +120,7 @@ if.then3.i394: ; preds = %if.end5.i362
br label %if.end5.i400
if.end5.i400: ; preds = %if.then3.i394, %if.end5.i362
- %pS.addr.0.i395 = phi ptr addrspace(5) [ %arrayidx232250.1, %if.then3.i394 ], [ undef, %if.end5.i362 ]
+ %pS.addr.0.i395 = phi ptr addrspace(5) [ %arrayidx232250.1, %if.then3.i394 ], [ poison, %if.end5.i362 ]
%7 = load i8, ptr addrspace(5) %pS.addr.0.i395, align 1
%conv612.i397 = sext i8 %7 to i32
%sub13.i398 = add nsw i32 %conv612.i397, -48
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll b/llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll
index 9b7d851a0c74e..a4cb43e14c2e2 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll
@@ -17,8 +17,8 @@ bb:
br label %bb1
bb1: ...
[truncated]
|
You can test this locally with the following command:git diff -U0 --pickaxe-regex -S '([^a-zA-Z0-9#_-]undef[^a-zA-Z0-9_-]|UndefValue::get)' 90e421516ee29ed475a052d0f5e96c2447e700d7 5ae18e53270678308066ae7e1ac9e84c346cb966 llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-break-large-phis.ll llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll llvm/test/CodeGen/AMDGPU/branch-relaxation.ll llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll llvm/test/CodeGen/AMDGPU/fold-fabs.ll llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll llvm/test/CodeGen/AMDGPU/inline-asm.ll llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll llvm/test/CodeGen/AMDGPU/madmk.ll llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll llvm/test/CodeGen/AMDGPU/multilevel-break.ll llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll llvm/test/CodeGen/AMDGPU/rewrite-undef-for-phi.ll llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll llvm/test/CodeGen/AMDGPU/select-undef.ll llvm/test/CodeGen/AMDGPU/si-spill-cf.ll llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll llvm/test/CodeGen/AMDGPU/skip-if-dead.ll llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll llvm/test/CodeGen/AMDGPU/switch-default-block-unreachable.ll llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll llvm/test/CodeGen/AMDGPU/uniform-phi-with-undef.ll llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll llvm/test/CodeGen/AMDGPU/wave32.llThe following files introduce new uses of undef:
Undef is now deprecated and should only be used in the rare cases where no replacement is possible. For example, a load of uninitialized memory yields In tests, avoid using For example, this is considered a bad practice: define void @fn() {
...
br i1 undef, ...
}Please use the following instead: define void @fn(i1 %cond) {
...
br i1 %cond, ...
}Please refer to the Undefined Behavior Manual for more information. |
|
Looks great, thank you! |
I think the chance of this changing the tests in meaningful ways is very low. This was perl with a few minor adjustments to a few tests that produce new undefs. Only one test had a minor codegen change with the switch, which I dropped from the change.
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shiltian
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Mar 7, 2025
|
Failing on a test this didn't touch |
arsenm
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I think the chance of this changing the tests in meaningful ways
is very low. This was perl with a few minor adjustments to a few
tests that produce new undefs. Only one test had a minor codegen
change with the switch, which I dropped from the change.