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[LLVM][AArch64] Add assembly/disassembly for SVE Integer Unary Arithm… (#113670)
…etic Predicated instructions This patch adds the following instructions: SVE bitwise unary operations (predicated) CLS, CLZ, CNT, CNOT, FABS, FNEG, NOT SVE integer unary operations (predicated) SXT{B,H,W}, UXT{B,H,W}, ABS ,NEG SVE2 integer unary operations (predicated) URECPE, URSQRTE, SQABS, SQNEG According to https://developer.arm.com/documentation/ddi0602 Co-authored-by: Spencer Abson [email protected]
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‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 37 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -647,22 +647,22 @@ let Predicates = [HasSVEorSME] in {
647647
defm SDOT_ZZZI : sve_intx_dot_by_indexed_elem<0b0, "sdot", int_aarch64_sve_sdot_lane>;
648648
defm UDOT_ZZZI : sve_intx_dot_by_indexed_elem<0b1, "udot", int_aarch64_sve_udot_lane>;
649649

650-
defm SXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b000, "sxtb", AArch64sxt_mt>;
651-
defm UXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b001, "uxtb", AArch64uxt_mt>;
652-
defm SXTH_ZPmZ : sve_int_un_pred_arit_0_w<0b010, "sxth", AArch64sxt_mt>;
653-
defm UXTH_ZPmZ : sve_int_un_pred_arit_0_w<0b011, "uxth", AArch64uxt_mt>;
654-
defm SXTW_ZPmZ : sve_int_un_pred_arit_0_d<0b100, "sxtw", AArch64sxt_mt>;
655-
defm UXTW_ZPmZ : sve_int_un_pred_arit_0_d<0b101, "uxtw", AArch64uxt_mt>;
656-
defm ABS_ZPmZ : sve_int_un_pred_arit_0< 0b110, "abs", AArch64abs_mt>;
657-
defm NEG_ZPmZ : sve_int_un_pred_arit_0< 0b111, "neg", AArch64neg_mt>;
658-
659-
defm CLS_ZPmZ : sve_int_un_pred_arit_1< 0b000, "cls", AArch64cls_mt>;
660-
defm CLZ_ZPmZ : sve_int_un_pred_arit_1< 0b001, "clz", AArch64clz_mt>;
661-
defm CNT_ZPmZ : sve_int_un_pred_arit_1< 0b010, "cnt", AArch64cnt_mt>;
662-
defm CNOT_ZPmZ : sve_int_un_pred_arit_1< 0b011, "cnot", AArch64cnot_mt>;
663-
defm NOT_ZPmZ : sve_int_un_pred_arit_1< 0b110, "not", AArch64not_mt>;
664-
defm FABS_ZPmZ : sve_int_un_pred_arit_1_fp<0b100, "fabs", AArch64fabs_mt>;
665-
defm FNEG_ZPmZ : sve_int_un_pred_arit_1_fp<0b101, "fneg", AArch64fneg_mt>;
650+
defm SXTB_ZPmZ : sve_int_un_pred_arit_h<0b000, "sxtb", AArch64sxt_mt>;
651+
defm UXTB_ZPmZ : sve_int_un_pred_arit_h<0b001, "uxtb", AArch64uxt_mt>;
652+
defm SXTH_ZPmZ : sve_int_un_pred_arit_w<0b010, "sxth", AArch64sxt_mt>;
653+
defm UXTH_ZPmZ : sve_int_un_pred_arit_w<0b011, "uxth", AArch64uxt_mt>;
654+
defm SXTW_ZPmZ : sve_int_un_pred_arit_d<0b100, "sxtw", AArch64sxt_mt>;
655+
defm UXTW_ZPmZ : sve_int_un_pred_arit_d<0b101, "uxtw", AArch64uxt_mt>;
656+
defm ABS_ZPmZ : sve_int_un_pred_arit< 0b110, "abs", AArch64abs_mt>;
657+
defm NEG_ZPmZ : sve_int_un_pred_arit< 0b111, "neg", AArch64neg_mt>;
658+
659+
defm CLS_ZPmZ : sve_int_un_pred_arit_bitwise< 0b000, "cls", AArch64cls_mt>;
660+
defm CLZ_ZPmZ : sve_int_un_pred_arit_bitwise< 0b001, "clz", AArch64clz_mt>;
661+
defm CNT_ZPmZ : sve_int_un_pred_arit_bitwise< 0b010, "cnt", AArch64cnt_mt>;
662+
defm CNOT_ZPmZ : sve_int_un_pred_arit_bitwise< 0b011, "cnot", AArch64cnot_mt>;
663+
defm NOT_ZPmZ : sve_int_un_pred_arit_bitwise< 0b110, "not", AArch64not_mt>;
664+
defm FABS_ZPmZ : sve_int_un_pred_arit_bitwise_fp<0b100, "fabs", AArch64fabs_mt>;
665+
defm FNEG_ZPmZ : sve_int_un_pred_arit_bitwise_fp<0b101, "fneg", AArch64fneg_mt>;
666666

667667
foreach VT = [nxv2bf16, nxv4bf16, nxv8bf16] in {
668668
// No dedicated instruction, so just clear the sign bit.
@@ -4271,6 +4271,27 @@ let Predicates = [HasSVE2p2orSME2p2] in {
42714271
// Floating-point square root, zeroing predicate
42724272
defm FSQRT_ZPZz : sve_fp_z2op_p_zd_hsd<0b01101, "fsqrt">;
42734273

4274+
// SVE2p2 integer unary arithmetic (bitwise), zeroing predicate
4275+
defm CLS_ZPzZ : sve_int_un_pred_arit_bitwise_z<0b000, "cls">;
4276+
defm CLZ_ZPzZ : sve_int_un_pred_arit_bitwise_z<0b001, "clz">;
4277+
defm CNT_ZPzZ : sve_int_un_pred_arit_bitwise_z<0b010, "cnt">;
4278+
defm CNOT_ZPzZ : sve_int_un_pred_arit_bitwise_z<0b011, "cnot">;
4279+
defm NOT_ZPzZ : sve_int_un_pred_arit_bitwise_z<0b110, "not">;
4280+
4281+
// floating point
4282+
defm FABS_ZPzZ : sve_int_un_pred_arit_bitwise_fp_z<0b100, "fabs">;
4283+
defm FNEG_ZPzZ : sve_int_un_pred_arit_bitwise_fp_z<0b101, "fneg">;
4284+
4285+
// SVE2p2 integer unary arithmetic, zeroing predicate
4286+
defm SXTB_ZPzZ : sve_int_un_pred_arit_h_z<0b000, "sxtb">;
4287+
defm UXTB_ZPzZ : sve_int_un_pred_arit_h_z<0b001, "uxtb">;
4288+
defm SXTH_ZPzZ : sve_int_un_pred_arit_w_z<0b010, "sxth">;
4289+
defm UXTH_ZPzZ : sve_int_un_pred_arit_w_z<0b011, "uxth">;
4290+
defm ABS_ZPzZ : sve_int_un_pred_arit_z< 0b110, "abs">;
4291+
defm NEG_ZPzZ : sve_int_un_pred_arit_z< 0b111, "neg">;
4292+
def SXTW_ZPzZ_D : sve_int_un_pred_arit_z<0b11, 0b1000, "sxtw", ZPR64>;
4293+
def UXTW_ZPzZ_D : sve_int_un_pred_arit_z<0b11, 0b1010, "uxtw", ZPR64>;
4294+
42744295
} // End HasSME2p2orSVE2p2
42754296

42764297
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 65 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -4685,8 +4685,30 @@ class sve_int_un_pred_arit<bits<2> sz8_64, bits<4> opc,
46854685
let hasSideEffects = 0;
46864686
}
46874687

4688-
multiclass sve_int_un_pred_arit_0<bits<3> opc, string asm,
4689-
SDPatternOperator op> {
4688+
class sve_int_un_pred_arit_z<bits<2> sz8_64, bits<4> opc,
4689+
string asm, ZPRRegOp zprty>
4690+
: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn),
4691+
asm, "\t$Zd, $Pg/z, $Zn",
4692+
"",
4693+
[]>, Sched<[]> {
4694+
bits<3> Pg;
4695+
bits<5> Zd;
4696+
bits<5> Zn;
4697+
let Inst{31-24} = 0b00000100;
4698+
let Inst{23-22} = sz8_64;
4699+
let Inst{21-20} = 0b00;
4700+
let Inst{19} = opc{0};
4701+
let Inst{18-16} = opc{3-1};
4702+
let Inst{15-13} = 0b101;
4703+
let Inst{12-10} = Pg;
4704+
let Inst{9-5} = Zn;
4705+
let Inst{4-0} = Zd;
4706+
4707+
let hasSideEffects = 0;
4708+
}
4709+
4710+
multiclass sve_int_un_pred_arit<bits<3> opc, string asm,
4711+
SDPatternOperator op> {
46904712
def _B : sve_int_un_pred_arit<0b00, { opc, 0b0 }, asm, ZPR8>,
46914713
SVEPseudo2Instr<NAME # _B, 1>;
46924714
def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>,
@@ -4712,8 +4734,15 @@ multiclass sve_int_un_pred_arit_0<bits<3> opc, string asm,
47124734
defm : SVE_1_Op_PassthruUndef_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Pseudo>(NAME # _D_UNDEF)>;
47134735
}
47144736

4715-
multiclass sve_int_un_pred_arit_0_h<bits<3> opc, string asm,
4716-
SDPatternOperator op> {
4737+
multiclass sve_int_un_pred_arit_z<bits<3> opc, string asm> {
4738+
def _B : sve_int_un_pred_arit_z<0b00, { opc, 0b0 }, asm, ZPR8>;
4739+
def _H : sve_int_un_pred_arit_z<0b01, { opc, 0b0 }, asm, ZPR16>;
4740+
def _S : sve_int_un_pred_arit_z<0b10, { opc, 0b0 }, asm, ZPR32>;
4741+
def _D : sve_int_un_pred_arit_z<0b11, { opc, 0b0 }, asm, ZPR64>;
4742+
}
4743+
4744+
multiclass sve_int_un_pred_arit_h<bits<3> opc, string asm,
4745+
SDPatternOperator op> {
47174746
def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>,
47184747
SVEPseudo2Instr<NAME # _H, 1>;
47194748
def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>,
@@ -4734,8 +4763,14 @@ multiclass sve_int_un_pred_arit_0_h<bits<3> opc, string asm,
47344763
defm : SVE_InReg_Extend_PassthruUndef<nxv2i64, op, nxv2i1, nxv2i8, !cast<Pseudo>(NAME # _D_UNDEF)>;
47354764
}
47364765

4737-
multiclass sve_int_un_pred_arit_0_w<bits<3> opc, string asm,
4738-
SDPatternOperator op> {
4766+
multiclass sve_int_un_pred_arit_h_z<bits<3> opc, string asm> {
4767+
def _H : sve_int_un_pred_arit_z<0b01, { opc, 0b0 }, asm, ZPR16>;
4768+
def _S : sve_int_un_pred_arit_z<0b10, { opc, 0b0 }, asm, ZPR32>;
4769+
def _D : sve_int_un_pred_arit_z<0b11, { opc, 0b0 }, asm, ZPR64>;
4770+
}
4771+
4772+
multiclass sve_int_un_pred_arit_w<bits<3> opc, string asm,
4773+
SDPatternOperator op> {
47394774
def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>,
47404775
SVEPseudo2Instr<NAME # _S, 1>;
47414776
def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>,
@@ -4751,8 +4786,13 @@ multiclass sve_int_un_pred_arit_0_w<bits<3> opc, string asm,
47514786
defm : SVE_InReg_Extend_PassthruUndef<nxv2i64, op, nxv2i1, nxv2i16, !cast<Pseudo>(NAME # _D_UNDEF)>;
47524787
}
47534788

4754-
multiclass sve_int_un_pred_arit_0_d<bits<3> opc, string asm,
4755-
SDPatternOperator op> {
4789+
multiclass sve_int_un_pred_arit_w_z<bits<3> opc, string asm> {
4790+
def _S : sve_int_un_pred_arit_z<0b10, { opc, 0b0 }, asm, ZPR32>;
4791+
def _D : sve_int_un_pred_arit_z<0b11, { opc, 0b0 }, asm, ZPR64>;
4792+
}
4793+
4794+
multiclass sve_int_un_pred_arit_d<bits<3> opc, string asm,
4795+
SDPatternOperator op> {
47564796
def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>,
47574797
SVEPseudo2Instr<NAME # _D, 1>;
47584798

@@ -4763,8 +4803,8 @@ multiclass sve_int_un_pred_arit_0_d<bits<3> opc, string asm,
47634803
defm : SVE_InReg_Extend_PassthruUndef<nxv2i64, op, nxv2i1, nxv2i32, !cast<Pseudo>(NAME # _D_UNDEF)>;
47644804
}
47654805

4766-
multiclass sve_int_un_pred_arit_1<bits<3> opc, string asm,
4767-
SDPatternOperator op> {
4806+
multiclass sve_int_un_pred_arit_bitwise<bits<3> opc, string asm,
4807+
SDPatternOperator op> {
47684808
def _B : sve_int_un_pred_arit<0b00, { opc, 0b1 }, asm, ZPR8>,
47694809
SVEPseudo2Instr<NAME # _B, 1>;
47704810
def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>,
@@ -4790,7 +4830,15 @@ multiclass sve_int_un_pred_arit_1<bits<3> opc, string asm,
47904830
defm : SVE_1_Op_PassthruUndef_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Pseudo>(NAME # _D_UNDEF)>;
47914831
}
47924832

4793-
multiclass sve_int_un_pred_arit_1_fp<bits<3> opc, string asm, SDPatternOperator op> {
4833+
multiclass sve_int_un_pred_arit_bitwise_z<bits<3> opc, string asm> {
4834+
def _B : sve_int_un_pred_arit_z<0b00, { opc, 0b1 }, asm, ZPR8>;
4835+
def _H : sve_int_un_pred_arit_z<0b01, { opc, 0b1 }, asm, ZPR16>;
4836+
def _S : sve_int_un_pred_arit_z<0b10, { opc, 0b1 }, asm, ZPR32>;
4837+
def _D : sve_int_un_pred_arit_z<0b11, { opc, 0b1 }, asm, ZPR64>;
4838+
}
4839+
4840+
multiclass sve_int_un_pred_arit_bitwise_fp<bits<3> opc, string asm,
4841+
SDPatternOperator op> {
47944842
def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>,
47954843
SVEPseudo2Instr<NAME # _H, 1>;
47964844
def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>,
@@ -4817,6 +4865,12 @@ multiclass sve_int_un_pred_arit_1_fp<bits<3> opc, string asm, SDPatternOperator
48174865
defm : SVE_1_Op_PassthruUndef_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Pseudo>(NAME # _D_UNDEF)>;
48184866
}
48194867

4868+
multiclass sve_int_un_pred_arit_bitwise_fp_z<bits<3> opc, string asm> {
4869+
def _H : sve_int_un_pred_arit_z<0b01, { opc, 0b1 }, asm, ZPR16>;
4870+
def _S : sve_int_un_pred_arit_z<0b10, { opc, 0b1 }, asm, ZPR32>;
4871+
def _D : sve_int_un_pred_arit_z<0b11, { opc, 0b1 }, asm, ZPR64>;
4872+
}
4873+
48204874
//===----------------------------------------------------------------------===//
48214875
// SVE Integer Wide Immediate - Unpredicated Group
48224876
//===----------------------------------------------------------------------===//

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