fixup! [RISCV] RISCV vector calling convention (1/2)

Author: 4vtomat

clang/include/clang/Basic/AttrDocs.td

@@ -5440,7 +5440,7 @@ def RISCVVectorCCDocs : Documentation {
 The ``riscv_vector_cc`` attribute can be applied to a function. It preserves 15
 registers namely, v1-v7 and v24-v31 as callee-saved. Callers thus don't need
 to save these registers before function calls, and callees only need to save
-them only if they use them.
+them if they use them.
  }];
 }
 

clang/test/CodeGen/RISCV/riscv-vector-callingconv.cpp

@@ -1,4 +1,3 @@
-// REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 %s -triple riscv64 -target-feature +v -verify
 
 __attribute__((riscv_vector_cc)) int var; // expected-warning {{'riscv_vector_cc' only applies to function types; type here is 'int'}}

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

@@ -640,7 +640,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
   // directives.
   for (const auto &Entry : CSI) {
     int FrameIdx = Entry.getFrameIdx();
-    if (FrameIdx >=0 &&
+    if (FrameIdx >= 0 &&
         MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector)
       continue;
 
@@ -1651,37 +1651,11 @@ bool RISCVFrameLowering::restoreCalleeSavedRegisters(
     DL = MI->getDebugLoc();
 
   // Manually restore values not restored by libcall & Push/Pop.
-  // Keep the same order as in the prologue. There is no need to reverse the
-  // order in the epilogue. In addition, the return address will be restored
-  // first in the epilogue. It increases the opportunity to avoid the
-  // load-to-use data hazard between loading RA and return by RA.
-  // loadRegFromStackSlot can insert multiple instructions.
-  //
-  //
-  // We first change the restore order for scalar and vector
-  // callee-saved registers as the layout shown below:
-  //
-  // Epilog restore order (original):
-  //     ----------------------------
-  //      RVV objects
-  //     ----------------------------
-  //      Callee-saved regs(scalar)
-  //      Callee-saved regs(vector)
-  //     ----------------------------
-  //
-  // Epilog restore order (after):
-  //     ----------------------------
-  //      RVV objects
-  //     ----------------------------
-  //      Callee-saved regs(vector)
-  //      Callee-saved regs(scalar)
-  //     ----------------------------
-  //
-  // So that it is able to put all vector registers which need
-  // to be restored together. The return address will be restored
-  // first in the scalar regs. It increases the opportunity to avoid the
-  // load-to-use data hazard between loading RA and return by RA.
-  // loadRegFromStackSlot can insert multiple instructions.
+  // Reverse the restore order in epilog.  In addition, the return
+  // address will be restored first in the epilogue. It increases
+  // the opportunity to avoid the load-to-use data hazard between
+  // loading RA and return by RA.  loadRegFromStackSlot can insert
+  // multiple instructions.
   const auto &UnmanagedCSI = getUnmanagedCSI(*MF, CSI);
   const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, CSI);