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[RISCV][SDAG] Improve codegen of select with constants if zicond is available
1 parent 0adba1b commit 929308f

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2 files changed

+80
-109
lines changed

2 files changed

+80
-109
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7379,6 +7379,26 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
73797379
if (SDValue V = combineSelectToBinOp(Op.getNode(), DAG, Subtarget))
73807380
return V;
73817381

7382+
// (select c, c1, c2) -> (add (czero_nez c2 - c1, c), c1)
7383+
// (select c, c1, c2) -> (add (czero_eqz c1 - c2, c), c2)
7384+
if (isa<ConstantSDNode>(TrueV) && isa<ConstantSDNode>(FalseV)) {
7385+
const APInt &TrueVal = TrueV->getAsAPIntVal();
7386+
const APInt &FalseVal = FalseV->getAsAPIntVal();
7387+
const int TrueValCost = RISCVMatInt::getIntMatCost(
7388+
TrueVal, Subtarget.getXLen(), Subtarget, /*CompressionCost=*/true);
7389+
const int FalseValCost = RISCVMatInt::getIntMatCost(
7390+
FalseVal, Subtarget.getXLen(), Subtarget, /*CompressionCost=*/true);
7391+
bool IsCZERO_NEZ = TrueValCost <= FalseValCost;
7392+
SDValue LHSVal = DAG.getConstant(
7393+
IsCZERO_NEZ ? FalseVal - TrueVal : TrueVal - FalseVal, DL, VT);
7394+
SDValue RHSVal =
7395+
DAG.getConstant(IsCZERO_NEZ ? TrueVal : FalseVal, DL, VT);
7396+
SDValue CMOV =
7397+
DAG.getNode(IsCZERO_NEZ ? RISCVISD::CZERO_NEZ : RISCVISD::CZERO_EQZ,
7398+
DL, VT, LHSVal, CondV);
7399+
return DAG.getNode(ISD::ADD, DL, VT, CMOV, RHSVal);
7400+
}
7401+
73827402
// (select c, t, f) -> (or (czero_eqz t, c), (czero_nez f, c))
73837403
// Unless we have the short forward branch optimization.
73847404
if (!Subtarget.hasConditionalMoveFusion())

‎llvm/test/CodeGen/RISCV/select.ll

Lines changed: 60 additions & 109 deletions
Original file line numberDiff line numberDiff line change
@@ -1606,21 +1606,17 @@ define i32 @select_cst_unknown(i32 signext %a, i32 signext %b) {
16061606
; RV64IMXVTCONDOPS-LABEL: select_cst_unknown:
16071607
; RV64IMXVTCONDOPS: # %bb.0:
16081608
; RV64IMXVTCONDOPS-NEXT: slt a0, a0, a1
1609-
; RV64IMXVTCONDOPS-NEXT: li a1, -7
1610-
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a0
1611-
; RV64IMXVTCONDOPS-NEXT: li a2, 5
1612-
; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a2, a0
1613-
; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1
1609+
; RV64IMXVTCONDOPS-NEXT: li a1, -12
1610+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
1611+
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 5
16141612
; RV64IMXVTCONDOPS-NEXT: ret
16151613
;
16161614
; CHECKZICOND-LABEL: select_cst_unknown:
16171615
; CHECKZICOND: # %bb.0:
16181616
; CHECKZICOND-NEXT: slt a0, a0, a1
1619-
; CHECKZICOND-NEXT: li a1, -7
1620-
; CHECKZICOND-NEXT: czero.nez a1, a1, a0
1621-
; CHECKZICOND-NEXT: li a2, 5
1622-
; CHECKZICOND-NEXT: czero.eqz a0, a2, a0
1623-
; CHECKZICOND-NEXT: or a0, a0, a1
1617+
; CHECKZICOND-NEXT: li a1, -12
1618+
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
1619+
; CHECKZICOND-NEXT: addi a0, a0, 5
16241620
; CHECKZICOND-NEXT: ret
16251621
%cond = icmp slt i32 %a, %b
16261622
%ret = select i1 %cond, i32 5, i32 -7
@@ -1650,20 +1646,16 @@ define i32 @select_cst1(i1 zeroext %cond) {
16501646
;
16511647
; RV64IMXVTCONDOPS-LABEL: select_cst1:
16521648
; RV64IMXVTCONDOPS: # %bb.0:
1653-
; RV64IMXVTCONDOPS-NEXT: li a1, 20
1654-
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a0
1655-
; RV64IMXVTCONDOPS-NEXT: li a2, 10
1656-
; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a2, a0
1657-
; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1
1649+
; RV64IMXVTCONDOPS-NEXT: li a1, 10
1650+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
1651+
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 10
16581652
; RV64IMXVTCONDOPS-NEXT: ret
16591653
;
16601654
; CHECKZICOND-LABEL: select_cst1:
16611655
; CHECKZICOND: # %bb.0:
1662-
; CHECKZICOND-NEXT: li a1, 20
1663-
; CHECKZICOND-NEXT: czero.nez a1, a1, a0
1664-
; CHECKZICOND-NEXT: li a2, 10
1665-
; CHECKZICOND-NEXT: czero.eqz a0, a2, a0
1666-
; CHECKZICOND-NEXT: or a0, a0, a1
1656+
; CHECKZICOND-NEXT: li a1, 10
1657+
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
1658+
; CHECKZICOND-NEXT: addi a0, a0, 10
16671659
; CHECKZICOND-NEXT: ret
16681660
%ret = select i1 %cond, i32 10, i32 20
16691661
ret i32 %ret
@@ -1694,32 +1686,26 @@ define i32 @select_cst2(i1 zeroext %cond) {
16941686
;
16951687
; RV64IMXVTCONDOPS-LABEL: select_cst2:
16961688
; RV64IMXVTCONDOPS: # %bb.0:
1697-
; RV64IMXVTCONDOPS-NEXT: li a1, 10
1698-
; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a0
1699-
; RV64IMXVTCONDOPS-NEXT: lui a2, 5
1700-
; RV64IMXVTCONDOPS-NEXT: addiw a2, a2, -480
1701-
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0
1702-
; RV64IMXVTCONDOPS-NEXT: or a0, a1, a0
1689+
; RV64IMXVTCONDOPS-NEXT: lui a1, 5
1690+
; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, -490
1691+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
1692+
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 10
17031693
; RV64IMXVTCONDOPS-NEXT: ret
17041694
;
17051695
; RV32IMZICOND-LABEL: select_cst2:
17061696
; RV32IMZICOND: # %bb.0:
1707-
; RV32IMZICOND-NEXT: li a1, 10
1708-
; RV32IMZICOND-NEXT: czero.eqz a1, a1, a0
1709-
; RV32IMZICOND-NEXT: lui a2, 5
1710-
; RV32IMZICOND-NEXT: addi a2, a2, -480
1711-
; RV32IMZICOND-NEXT: czero.nez a0, a2, a0
1712-
; RV32IMZICOND-NEXT: or a0, a1, a0
1697+
; RV32IMZICOND-NEXT: lui a1, 5
1698+
; RV32IMZICOND-NEXT: addi a1, a1, -490
1699+
; RV32IMZICOND-NEXT: czero.nez a0, a1, a0
1700+
; RV32IMZICOND-NEXT: addi a0, a0, 10
17131701
; RV32IMZICOND-NEXT: ret
17141702
;
17151703
; RV64IMZICOND-LABEL: select_cst2:
17161704
; RV64IMZICOND: # %bb.0:
1717-
; RV64IMZICOND-NEXT: li a1, 10
1718-
; RV64IMZICOND-NEXT: czero.eqz a1, a1, a0
1719-
; RV64IMZICOND-NEXT: lui a2, 5
1720-
; RV64IMZICOND-NEXT: addiw a2, a2, -480
1721-
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
1722-
; RV64IMZICOND-NEXT: or a0, a1, a0
1705+
; RV64IMZICOND-NEXT: lui a1, 5
1706+
; RV64IMZICOND-NEXT: addiw a1, a1, -490
1707+
; RV64IMZICOND-NEXT: czero.nez a0, a1, a0
1708+
; RV64IMZICOND-NEXT: addi a0, a0, 10
17231709
; RV64IMZICOND-NEXT: ret
17241710
%ret = select i1 %cond, i32 10, i32 20000
17251711
ret i32 %ret
@@ -1752,35 +1738,32 @@ define i32 @select_cst3(i1 zeroext %cond) {
17521738
;
17531739
; RV64IMXVTCONDOPS-LABEL: select_cst3:
17541740
; RV64IMXVTCONDOPS: # %bb.0:
1755-
; RV64IMXVTCONDOPS-NEXT: lui a1, 5
1756-
; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, -480
1757-
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a0
1758-
; RV64IMXVTCONDOPS-NEXT: lui a2, 7
1759-
; RV64IMXVTCONDOPS-NEXT: addiw a2, a2, 1328
1760-
; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a2, a0
1761-
; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1
1741+
; RV64IMXVTCONDOPS-NEXT: lui a1, 1048574
1742+
; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, -1808
1743+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
1744+
; RV64IMXVTCONDOPS-NEXT: lui a1, 7
1745+
; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, 1328
1746+
; RV64IMXVTCONDOPS-NEXT: add a0, a0, a1
17621747
; RV64IMXVTCONDOPS-NEXT: ret
17631748
;
17641749
; RV32IMZICOND-LABEL: select_cst3:
17651750
; RV32IMZICOND: # %bb.0:
1766-
; RV32IMZICOND-NEXT: lui a1, 5
1767-
; RV32IMZICOND-NEXT: addi a1, a1, -480
1768-
; RV32IMZICOND-NEXT: czero.nez a1, a1, a0
1769-
; RV32IMZICOND-NEXT: lui a2, 7
1770-
; RV32IMZICOND-NEXT: addi a2, a2, 1328
1771-
; RV32IMZICOND-NEXT: czero.eqz a0, a2, a0
1772-
; RV32IMZICOND-NEXT: or a0, a0, a1
1751+
; RV32IMZICOND-NEXT: lui a1, 1048574
1752+
; RV32IMZICOND-NEXT: addi a1, a1, -1808
1753+
; RV32IMZICOND-NEXT: czero.nez a0, a1, a0
1754+
; RV32IMZICOND-NEXT: lui a1, 7
1755+
; RV32IMZICOND-NEXT: addi a1, a1, 1328
1756+
; RV32IMZICOND-NEXT: add a0, a0, a1
17731757
; RV32IMZICOND-NEXT: ret
17741758
;
17751759
; RV64IMZICOND-LABEL: select_cst3:
17761760
; RV64IMZICOND: # %bb.0:
1777-
; RV64IMZICOND-NEXT: lui a1, 5
1778-
; RV64IMZICOND-NEXT: addiw a1, a1, -480
1779-
; RV64IMZICOND-NEXT: czero.nez a1, a1, a0
1780-
; RV64IMZICOND-NEXT: lui a2, 7
1781-
; RV64IMZICOND-NEXT: addiw a2, a2, 1328
1782-
; RV64IMZICOND-NEXT: czero.eqz a0, a2, a0
1783-
; RV64IMZICOND-NEXT: or a0, a0, a1
1761+
; RV64IMZICOND-NEXT: lui a1, 1048574
1762+
; RV64IMZICOND-NEXT: addiw a1, a1, -1808
1763+
; RV64IMZICOND-NEXT: czero.nez a0, a1, a0
1764+
; RV64IMZICOND-NEXT: lui a1, 7
1765+
; RV64IMZICOND-NEXT: addiw a1, a1, 1328
1766+
; RV64IMZICOND-NEXT: add a0, a0, a1
17841767
; RV64IMZICOND-NEXT: ret
17851768
%ret = select i1 %cond, i32 30000, i32 20000
17861769
ret i32 %ret
@@ -1821,33 +1804,17 @@ define i32 @select_cst5(i1 zeroext %cond) {
18211804
;
18221805
; RV64IMXVTCONDOPS-LABEL: select_cst5:
18231806
; RV64IMXVTCONDOPS: # %bb.0:
1824-
; RV64IMXVTCONDOPS-NEXT: li a1, 2047
1825-
; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a0
1826-
; RV64IMXVTCONDOPS-NEXT: lui a2, 1
1827-
; RV64IMXVTCONDOPS-NEXT: addiw a2, a2, -2047
1828-
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0
1829-
; RV64IMXVTCONDOPS-NEXT: or a0, a1, a0
1807+
; RV64IMXVTCONDOPS-NEXT: li a1, 2
1808+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
1809+
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 2047
18301810
; RV64IMXVTCONDOPS-NEXT: ret
18311811
;
1832-
; RV32IMZICOND-LABEL: select_cst5:
1833-
; RV32IMZICOND: # %bb.0:
1834-
; RV32IMZICOND-NEXT: li a1, 2047
1835-
; RV32IMZICOND-NEXT: czero.eqz a1, a1, a0
1836-
; RV32IMZICOND-NEXT: lui a2, 1
1837-
; RV32IMZICOND-NEXT: addi a2, a2, -2047
1838-
; RV32IMZICOND-NEXT: czero.nez a0, a2, a0
1839-
; RV32IMZICOND-NEXT: or a0, a1, a0
1840-
; RV32IMZICOND-NEXT: ret
1841-
;
1842-
; RV64IMZICOND-LABEL: select_cst5:
1843-
; RV64IMZICOND: # %bb.0:
1844-
; RV64IMZICOND-NEXT: li a1, 2047
1845-
; RV64IMZICOND-NEXT: czero.eqz a1, a1, a0
1846-
; RV64IMZICOND-NEXT: lui a2, 1
1847-
; RV64IMZICOND-NEXT: addiw a2, a2, -2047
1848-
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
1849-
; RV64IMZICOND-NEXT: or a0, a1, a0
1850-
; RV64IMZICOND-NEXT: ret
1812+
; CHECKZICOND-LABEL: select_cst5:
1813+
; CHECKZICOND: # %bb.0:
1814+
; CHECKZICOND-NEXT: li a1, 2
1815+
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
1816+
; CHECKZICOND-NEXT: addi a0, a0, 2047
1817+
; CHECKZICOND-NEXT: ret
18511818
%ret = select i1 %cond, i32 2047, i32 2049
18521819
ret i32 %ret
18531820
}
@@ -1877,33 +1844,17 @@ define i32 @select_cst6(i1 zeroext %cond) {
18771844
;
18781845
; RV64IMXVTCONDOPS-LABEL: select_cst6:
18791846
; RV64IMXVTCONDOPS: # %bb.0:
1880-
; RV64IMXVTCONDOPS-NEXT: li a1, 2047
1881-
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a0
1882-
; RV64IMXVTCONDOPS-NEXT: lui a2, 1
1883-
; RV64IMXVTCONDOPS-NEXT: addiw a2, a2, -2047
1884-
; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a2, a0
1885-
; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1
1847+
; RV64IMXVTCONDOPS-NEXT: li a1, 2
1848+
; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0
1849+
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 2047
18861850
; RV64IMXVTCONDOPS-NEXT: ret
18871851
;
1888-
; RV32IMZICOND-LABEL: select_cst6:
1889-
; RV32IMZICOND: # %bb.0:
1890-
; RV32IMZICOND-NEXT: li a1, 2047
1891-
; RV32IMZICOND-NEXT: czero.nez a1, a1, a0
1892-
; RV32IMZICOND-NEXT: lui a2, 1
1893-
; RV32IMZICOND-NEXT: addi a2, a2, -2047
1894-
; RV32IMZICOND-NEXT: czero.eqz a0, a2, a0
1895-
; RV32IMZICOND-NEXT: or a0, a0, a1
1896-
; RV32IMZICOND-NEXT: ret
1897-
;
1898-
; RV64IMZICOND-LABEL: select_cst6:
1899-
; RV64IMZICOND: # %bb.0:
1900-
; RV64IMZICOND-NEXT: li a1, 2047
1901-
; RV64IMZICOND-NEXT: czero.nez a1, a1, a0
1902-
; RV64IMZICOND-NEXT: lui a2, 1
1903-
; RV64IMZICOND-NEXT: addiw a2, a2, -2047
1904-
; RV64IMZICOND-NEXT: czero.eqz a0, a2, a0
1905-
; RV64IMZICOND-NEXT: or a0, a0, a1
1906-
; RV64IMZICOND-NEXT: ret
1852+
; CHECKZICOND-LABEL: select_cst6:
1853+
; CHECKZICOND: # %bb.0:
1854+
; CHECKZICOND-NEXT: li a1, 2
1855+
; CHECKZICOND-NEXT: czero.eqz a0, a1, a0
1856+
; CHECKZICOND-NEXT: addi a0, a0, 2047
1857+
; CHECKZICOND-NEXT: ret
19071858
%ret = select i1 %cond, i32 2049, i32 2047
19081859
ret i32 %ret
19091860
}

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