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1 parent 0988bf8 commit 935da49Copy full SHA for 935da49
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -319,7 +319,8 @@ struct SGPRSpillBuilder {
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SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST)
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: AMDGPUGenRegisterInfo(AMDGPU::PC_REG, ST.getAMDGPUDwarfFlavour(),
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- ST.getAMDGPUDwarfFlavour()),
+ ST.getAMDGPUDwarfFlavour(),
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+ /*PC=*/0, ST.getHwMode()),
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ST(ST), SpillSGPRToVGPR(EnableSpillSGPRToVGPR), isWave32(ST.isWave32()) {
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assert(getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() == 3 &&
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