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[RISCV] Split and expand test coverage for zipeven/zipodd shuffles [NFC]
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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll

Lines changed: 18 additions & 70 deletions
Original file line numberDiff line numberDiff line change
@@ -1005,63 +1005,11 @@ define <8 x i32> @shuffle_repeat4_singlesrc_e32(<8 x i32> %v) {
10051005
ret <8 x i32> %out
10061006
}
10071007

1008-
define <8 x i32> @shuffle_zipeven_v8i32(<8 x i32> %v1, <8 x i32> %v2) {
1009-
; CHECK-LABEL: shuffle_zipeven_v8i32:
1010-
; CHECK: # %bb.0:
1011-
; CHECK-NEXT: li a0, 170
1012-
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
1013-
; CHECK-NEXT: vmv.s.x v0, a0
1014-
; CHECK-NEXT: vslideup.vi v8, v10, 1, v0.t
1015-
; CHECK-NEXT: ret
1016-
%out = shufflevector <8 x i32> %v1, <8 x i32> %v2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
1017-
ret <8 x i32> %out
1018-
}
1019-
1020-
define <8 x i32> @shuffle_zipodd_v8i32(<8 x i32> %v1, <8 x i32> %v2) {
1021-
; CHECK-LABEL: shuffle_zipodd_v8i32:
1022-
; CHECK: # %bb.0:
1023-
; CHECK-NEXT: li a0, 85
1024-
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
1025-
; CHECK-NEXT: vmv.s.x v0, a0
1026-
; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
1027-
; CHECK-NEXT: vmv.v.v v8, v10
1028-
; CHECK-NEXT: ret
1029-
%out = shufflevector <8 x i32> %v1, <8 x i32> %v2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
1030-
ret <8 x i32> %out
1031-
}
1032-
1033-
define <16 x i64> @shuffle_zipeven_v16i64(<16 x i64> %v1, <16 x i64> %v2) {
1034-
; CHECK-LABEL: shuffle_zipeven_v16i64:
1035-
; CHECK: # %bb.0:
1036-
; CHECK-NEXT: lui a0, 11
1037-
; CHECK-NEXT: addi a0, a0, -1366
1038-
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
1039-
; CHECK-NEXT: vmv.s.x v0, a0
1040-
; CHECK-NEXT: vslideup.vi v8, v16, 1, v0.t
1041-
; CHECK-NEXT: ret
1042-
%out = shufflevector <16 x i64> %v1, <16 x i64> %v2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
1043-
ret <16 x i64> %out
1044-
}
1045-
1046-
define <16 x i64> @shuffle_zipodd_v16i64(<16 x i64> %v1, <16 x i64> %v2) {
1047-
; CHECK-LABEL: shuffle_zipodd_v16i64:
1048-
; CHECK: # %bb.0:
1049-
; CHECK-NEXT: lui a0, 5
1050-
; CHECK-NEXT: addi a0, a0, 1365
1051-
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
1052-
; CHECK-NEXT: vmv.s.x v0, a0
1053-
; CHECK-NEXT: vslidedown.vi v16, v8, 1, v0.t
1054-
; CHECK-NEXT: vmv.v.v v8, v16
1055-
; CHECK-NEXT: ret
1056-
%out = shufflevector <16 x i64> %v1, <16 x i64> %v2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
1057-
ret <16 x i64> %out
1058-
}
1059-
10601008
define <16 x i32> @shuffle_disjoint_lanes(<16 x i32> %v, <16 x i32> %w) {
10611009
; CHECK-LABEL: shuffle_disjoint_lanes:
10621010
; CHECK: # %bb.0:
1063-
; CHECK-NEXT: lui a0, %hi(.LCPI74_0)
1064-
; CHECK-NEXT: addi a0, a0, %lo(.LCPI74_0)
1011+
; CHECK-NEXT: lui a0, %hi(.LCPI70_0)
1012+
; CHECK-NEXT: addi a0, a0, %lo(.LCPI70_0)
10651013
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
10661014
; CHECK-NEXT: vle8.v v18, (a0)
10671015
; CHECK-NEXT: lui a0, 11
@@ -1080,8 +1028,8 @@ define <16 x i32> @shuffle_disjoint_lanes(<16 x i32> %v, <16 x i32> %w) {
10801028
define <16 x i32> @shuffle_disjoint_lanes_one_identity(<16 x i32> %v, <16 x i32> %w) {
10811029
; CHECK-LABEL: shuffle_disjoint_lanes_one_identity:
10821030
; CHECK: # %bb.0:
1083-
; CHECK-NEXT: lui a0, %hi(.LCPI75_0)
1084-
; CHECK-NEXT: addi a0, a0, %lo(.LCPI75_0)
1031+
; CHECK-NEXT: lui a0, %hi(.LCPI71_0)
1032+
; CHECK-NEXT: addi a0, a0, %lo(.LCPI71_0)
10851033
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
10861034
; CHECK-NEXT: vle16.v v16, (a0)
10871035
; CHECK-NEXT: li a0, -272
@@ -1095,8 +1043,8 @@ define <16 x i32> @shuffle_disjoint_lanes_one_identity(<16 x i32> %v, <16 x i32>
10951043
define <16 x i32> @shuffle_disjoint_lanes_one_broadcast(<16 x i32> %v, <16 x i32> %w) {
10961044
; CHECK-LABEL: shuffle_disjoint_lanes_one_broadcast:
10971045
; CHECK: # %bb.0:
1098-
; CHECK-NEXT: lui a0, %hi(.LCPI76_0)
1099-
; CHECK-NEXT: addi a0, a0, %lo(.LCPI76_0)
1046+
; CHECK-NEXT: lui a0, %hi(.LCPI72_0)
1047+
; CHECK-NEXT: addi a0, a0, %lo(.LCPI72_0)
11001048
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
11011049
; CHECK-NEXT: vle16.v v20, (a0)
11021050
; CHECK-NEXT: lui a0, 15
@@ -1113,8 +1061,8 @@ define <16 x i32> @shuffle_disjoint_lanes_one_broadcast(<16 x i32> %v, <16 x i32
11131061
define <16 x i32> @shuffle_disjoint_lanes_one_splat(i32 %v, <16 x i32> %w) {
11141062
; CHECK-LABEL: shuffle_disjoint_lanes_one_splat:
11151063
; CHECK: # %bb.0:
1116-
; CHECK-NEXT: lui a1, %hi(.LCPI77_0)
1117-
; CHECK-NEXT: addi a1, a1, %lo(.LCPI77_0)
1064+
; CHECK-NEXT: lui a1, %hi(.LCPI73_0)
1065+
; CHECK-NEXT: addi a1, a1, %lo(.LCPI73_0)
11181066
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
11191067
; CHECK-NEXT: vle16.v v16, (a1)
11201068
; CHECK-NEXT: lui a1, 15
@@ -1167,8 +1115,8 @@ define <4 x i128> @shuffle_i128(<4 x i128> %a) {
11671115
; RV32-NEXT: lw a1, 0(a1)
11681116
; RV32-NEXT: mv a2, sp
11691117
; RV32-NEXT: sw a1, 0(sp)
1170-
; RV32-NEXT: lui a1, %hi(.LCPI78_0)
1171-
; RV32-NEXT: addi a1, a1, %lo(.LCPI78_0)
1118+
; RV32-NEXT: lui a1, %hi(.LCPI74_0)
1119+
; RV32-NEXT: addi a1, a1, %lo(.LCPI74_0)
11721120
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
11731121
; RV32-NEXT: vle32.v v8, (a2)
11741122
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
@@ -1209,8 +1157,8 @@ define <4 x i128> @shuffle_i128(<4 x i128> %a) {
12091157
; RV64-NEXT: ld a1, 0(a1)
12101158
; RV64-NEXT: mv a2, sp
12111159
; RV64-NEXT: sd a1, 0(sp)
1212-
; RV64-NEXT: lui a1, %hi(.LCPI78_0)
1213-
; RV64-NEXT: addi a1, a1, %lo(.LCPI78_0)
1160+
; RV64-NEXT: lui a1, %hi(.LCPI74_0)
1161+
; RV64-NEXT: addi a1, a1, %lo(.LCPI74_0)
12141162
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
12151163
; RV64-NEXT: vle64.v v8, (a2)
12161164
; RV64-NEXT: vle16.v v16, (a1)
@@ -1234,8 +1182,8 @@ define void @shuffle_i128_ldst(ptr %p) {
12341182
; CHECK: # %bb.0:
12351183
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
12361184
; CHECK-NEXT: vle64.v v8, (a0)
1237-
; CHECK-NEXT: lui a1, %hi(.LCPI79_0)
1238-
; CHECK-NEXT: addi a1, a1, %lo(.LCPI79_0)
1185+
; CHECK-NEXT: lui a1, %hi(.LCPI75_0)
1186+
; CHECK-NEXT: addi a1, a1, %lo(.LCPI75_0)
12391187
; CHECK-NEXT: vle16.v v16, (a1)
12401188
; CHECK-NEXT: vrgatherei16.vv v12, v8, v16
12411189
; CHECK-NEXT: vse64.v v12, (a0)
@@ -1249,8 +1197,8 @@ define void @shuffle_i128_ldst(ptr %p) {
12491197
define void @shuffle_i256_ldst(ptr %p) {
12501198
; CHECK-LABEL: shuffle_i256_ldst:
12511199
; CHECK: # %bb.0:
1252-
; CHECK-NEXT: lui a1, %hi(.LCPI80_0)
1253-
; CHECK-NEXT: addi a1, a1, %lo(.LCPI80_0)
1200+
; CHECK-NEXT: lui a1, %hi(.LCPI76_0)
1201+
; CHECK-NEXT: addi a1, a1, %lo(.LCPI76_0)
12541202
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
12551203
; CHECK-NEXT: vle8.v v16, (a1)
12561204
; CHECK-NEXT: vle64.v v8, (a0)
@@ -1361,8 +1309,8 @@ define <16 x i32> @shuffle_m1_prefix(<16 x i32> %a) {
13611309
define <16 x i32> @shuffle_m2_prefix(<16 x i32> %a) {
13621310
; CHECK-LABEL: shuffle_m2_prefix:
13631311
; CHECK: # %bb.0:
1364-
; CHECK-NEXT: lui a0, %hi(.LCPI85_0)
1365-
; CHECK-NEXT: addi a0, a0, %lo(.LCPI85_0)
1312+
; CHECK-NEXT: lui a0, %hi(.LCPI81_0)
1313+
; CHECK-NEXT: addi a0, a0, %lo(.LCPI81_0)
13661314
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
13671315
; CHECK-NEXT: vle16.v v14, (a0)
13681316
; CHECK-NEXT: vrgatherei16.vv v12, v8, v14

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll

Lines changed: 243 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,243 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3+
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
4+
5+
define <4 x i32> @zipeven_v4i32(<4 x i32> %a, <4 x i32> %b) {
6+
; CHECK-LABEL: zipeven_v4i32:
7+
; CHECK: # %bb.0: # %entry
8+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
9+
; CHECK-NEXT: vmv.v.i v0, 10
10+
; CHECK-NEXT: vslideup.vi v8, v9, 1, v0.t
11+
; CHECK-NEXT: ret
12+
entry:
13+
%c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
14+
ret <4 x i32> %c
15+
}
16+
17+
define <4 x i32> @zipeven_v4i32_swapped(<4 x i32> %a, <4 x i32> %b) {
18+
; CHECK-LABEL: zipeven_v4i32_swapped:
19+
; CHECK: # %bb.0: # %entry
20+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
21+
; CHECK-NEXT: vmv.v.i v0, 10
22+
; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t
23+
; CHECK-NEXT: vmv.v.v v8, v9
24+
; CHECK-NEXT: ret
25+
entry:
26+
%c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 0, i32 6, i32 2>
27+
ret <4 x i32> %c
28+
}
29+
30+
define <4 x i64> @zipeven_v4i64(<4 x i64> %a, <4 x i64> %b) {
31+
; CHECK-LABEL: zipeven_v4i64:
32+
; CHECK: # %bb.0: # %entry
33+
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
34+
; CHECK-NEXT: vmv.v.i v0, 10
35+
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
36+
; CHECK-NEXT: vslideup.vi v8, v10, 1, v0.t
37+
; CHECK-NEXT: ret
38+
entry:
39+
%c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
40+
ret <4 x i64> %c
41+
}
42+
43+
define <4 x half> @zipeven_v4f16(<4 x half> %a, <4 x half> %b) {
44+
; RV32-LABEL: zipeven_v4f16:
45+
; RV32: # %bb.0: # %entry
46+
; RV32-NEXT: lh a3, 0(a1)
47+
; RV32-NEXT: lh a4, 0(a2)
48+
; RV32-NEXT: lh a1, 8(a1)
49+
; RV32-NEXT: lh a2, 8(a2)
50+
; RV32-NEXT: sh a3, 0(a0)
51+
; RV32-NEXT: sh a4, 2(a0)
52+
; RV32-NEXT: sh a1, 4(a0)
53+
; RV32-NEXT: sh a2, 6(a0)
54+
; RV32-NEXT: ret
55+
;
56+
; RV64-LABEL: zipeven_v4f16:
57+
; RV64: # %bb.0: # %entry
58+
; RV64-NEXT: lh a3, 0(a1)
59+
; RV64-NEXT: lh a4, 0(a2)
60+
; RV64-NEXT: lh a1, 16(a1)
61+
; RV64-NEXT: lh a2, 16(a2)
62+
; RV64-NEXT: sh a3, 0(a0)
63+
; RV64-NEXT: sh a4, 2(a0)
64+
; RV64-NEXT: sh a1, 4(a0)
65+
; RV64-NEXT: sh a2, 6(a0)
66+
; RV64-NEXT: ret
67+
entry:
68+
%c = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
69+
ret <4 x half> %c
70+
}
71+
72+
define <4 x float> @zipeven_v4f32(<4 x float> %a, <4 x float> %b) {
73+
; CHECK-LABEL: zipeven_v4f32:
74+
; CHECK: # %bb.0: # %entry
75+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
76+
; CHECK-NEXT: vmv.v.i v0, 10
77+
; CHECK-NEXT: vslideup.vi v8, v9, 1, v0.t
78+
; CHECK-NEXT: ret
79+
entry:
80+
%c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
81+
ret <4 x float> %c
82+
}
83+
84+
define <4 x double> @zipeven_v4f64(<4 x double> %a, <4 x double> %b) {
85+
; CHECK-LABEL: zipeven_v4f64:
86+
; CHECK: # %bb.0: # %entry
87+
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
88+
; CHECK-NEXT: vmv.v.i v0, 10
89+
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
90+
; CHECK-NEXT: vslideup.vi v8, v10, 1, v0.t
91+
; CHECK-NEXT: ret
92+
entry:
93+
%c = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
94+
ret <4 x double> %c
95+
}
96+
97+
98+
define <4 x i32> @zipodd_v4i32(<4 x i32> %a, <4 x i32> %b) {
99+
; CHECK-LABEL: zipodd_v4i32:
100+
; CHECK: # %bb.0: # %entry
101+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
102+
; CHECK-NEXT: vmv.v.i v0, 5
103+
; CHECK-NEXT: vslidedown.vi v9, v8, 1, v0.t
104+
; CHECK-NEXT: vmv.v.v v8, v9
105+
; CHECK-NEXT: ret
106+
entry:
107+
%c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
108+
ret <4 x i32> %c
109+
}
110+
111+
define <4 x i32> @zipodd_v4i32_swapped(<4 x i32> %a, <4 x i32> %b) {
112+
; CHECK-LABEL: zipodd_v4i32_swapped:
113+
; CHECK: # %bb.0: # %entry
114+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
115+
; CHECK-NEXT: vmv.v.i v0, 5
116+
; CHECK-NEXT: vslidedown.vi v8, v9, 1, v0.t
117+
; CHECK-NEXT: ret
118+
entry:
119+
%c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 1, i32 7, i32 3>
120+
ret <4 x i32> %c
121+
}
122+
123+
define <4 x i32> @zipeven_v4i32_single(<4 x i32> %a) {
124+
; CHECK-LABEL: zipeven_v4i32_single:
125+
; CHECK: # %bb.0: # %entry
126+
; CHECK-NEXT: ret
127+
entry:
128+
%c = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> <i32 0, i32 poison, i32 2, i32 poison>
129+
ret <4 x i32> %c
130+
}
131+
132+
define <4 x i32> @zipodd_v4i32_single(<4 x i32> %a) {
133+
; CHECK-LABEL: zipodd_v4i32_single:
134+
; CHECK: # %bb.0: # %entry
135+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
136+
; CHECK-NEXT: vslidedown.vi v8, v8, 1
137+
; CHECK-NEXT: ret
138+
entry:
139+
%c = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 3, i32 poison>
140+
ret <4 x i32> %c
141+
}
142+
143+
define <4 x i32> @zipodd_v4i32_both(<4 x i32> %a) {
144+
; CHECK-LABEL: zipodd_v4i32_both:
145+
; CHECK: # %bb.0: # %entry
146+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
147+
; CHECK-NEXT: vmv.v.i v0, 5
148+
; CHECK-NEXT: vslidedown.vi v8, v8, 1, v0.t
149+
; CHECK-NEXT: ret
150+
entry:
151+
%c = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
152+
ret <4 x i32> %c
153+
}
154+
155+
define <4 x i32> @zipeven_v4i32_both(<4 x i32> %a) {
156+
; CHECK-LABEL: zipeven_v4i32_both:
157+
; CHECK: # %bb.0: # %entry
158+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
159+
; CHECK-NEXT: vmv.v.i v0, 10
160+
; CHECK-NEXT: vmv1r.v v9, v8
161+
; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t
162+
; CHECK-NEXT: vmv.v.v v8, v9
163+
; CHECK-NEXT: ret
164+
entry:
165+
%c = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
166+
ret <4 x i32> %c
167+
}
168+
169+
define <4 x i32> @zipeven_v4i32_partial(<4 x i32> %a, <4 x i32> %b) {
170+
; CHECK-LABEL: zipeven_v4i32_partial:
171+
; CHECK: # %bb.0: # %entry
172+
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
173+
; CHECK-NEXT: vslideup.vi v8, v9, 1
174+
; CHECK-NEXT: ret
175+
entry:
176+
%c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 poison>
177+
ret <4 x i32> %c
178+
}
179+
180+
define <4 x i32> @zipodd_v4i32_partial(<4 x i32> %a, <4 x i32> %b) {
181+
; CHECK-LABEL: zipodd_v4i32_partial:
182+
; CHECK: # %bb.0: # %entry
183+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
184+
; CHECK-NEXT: vmv.v.i v0, 5
185+
; CHECK-NEXT: vslidedown.vi v9, v8, 1, v0.t
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; CHECK-NEXT: vmv.v.v v8, v9
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; CHECK-NEXT: ret
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entry:
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%c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 poison>
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ret <4 x i32> %c
191+
}
192+
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define <8 x i32> @zipeven_v8i32(<8 x i32> %v1, <8 x i32> %v2) {
194+
; CHECK-LABEL: zipeven_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a0, 170
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; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
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; CHECK-NEXT: vmv.s.x v0, a0
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; CHECK-NEXT: vslideup.vi v8, v10, 1, v0.t
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; CHECK-NEXT: ret
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%out = shufflevector <8 x i32> %v1, <8 x i32> %v2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
202+
ret <8 x i32> %out
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}
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define <8 x i32> @zipodd_v8i32(<8 x i32> %v1, <8 x i32> %v2) {
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; CHECK-LABEL: zipodd_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a0, 85
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; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
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; CHECK-NEXT: vmv.s.x v0, a0
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; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: ret
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%out = shufflevector <8 x i32> %v1, <8 x i32> %v2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
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ret <8 x i32> %out
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}
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define <16 x i64> @zipeven_v16i64(<16 x i64> %v1, <16 x i64> %v2) {
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; CHECK-LABEL: zipeven_v16i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 11
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; CHECK-NEXT: addi a0, a0, -1366
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; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
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; CHECK-NEXT: vmv.s.x v0, a0
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; CHECK-NEXT: vslideup.vi v8, v16, 1, v0.t
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; CHECK-NEXT: ret
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%out = shufflevector <16 x i64> %v1, <16 x i64> %v2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
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ret <16 x i64> %out
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}
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define <16 x i64> @zipodd_v16i64(<16 x i64> %v1, <16 x i64> %v2) {
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; CHECK-LABEL: zipodd_v16i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 5
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; CHECK-NEXT: addi a0, a0, 1365
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; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
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; CHECK-NEXT: vmv.s.x v0, a0
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; CHECK-NEXT: vslidedown.vi v16, v8, 1, v0.t
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; CHECK-NEXT: vmv.v.v v8, v16
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; CHECK-NEXT: ret
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%out = shufflevector <16 x i64> %v1, <16 x i64> %v2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
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ret <16 x i64> %out
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}

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