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arsenmarsenm
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GlobalISel: fewerElementsVector for a few more trivial ops
llvm-svn: 352165
1 parent 5d622fb commit 95fd95c

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8 files changed

+343
-5
lines changed

8 files changed

+343
-5
lines changed

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1407,6 +1407,12 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
14071407
case TargetOpcode::G_FDIV:
14081408
case TargetOpcode::G_FREM:
14091409
case TargetOpcode::G_FMA:
1410+
case TargetOpcode::G_FPOW:
1411+
case TargetOpcode::G_FEXP:
1412+
case TargetOpcode::G_FEXP2:
1413+
case TargetOpcode::G_FLOG:
1414+
case TargetOpcode::G_FLOG2:
1415+
case TargetOpcode::G_FLOG10:
14101416
case TargetOpcode::G_FCEIL: {
14111417
unsigned NarrowSize = NarrowTy.getSizeInBits();
14121418
unsigned DstReg = MI.getOperand(0).getReg();

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -176,10 +176,6 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
176176
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
177177
.legalFor({{S32, S32}, {S32, S64}});
178178

179-
setAction({G_FPOW, S32}, Legal);
180-
setAction({G_FEXP2, S32}, Legal);
181-
setAction({G_FLOG2, S32}, Legal);
182-
183179
getActionDefinitionsBuilder({G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND})
184180
.legalFor({S32, S64});
185181

@@ -198,7 +194,11 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
198194
.clampMaxNumElements(0, S1, 1)
199195
.clampMaxNumElements(1, S32, 1);
200196

201-
197+
// FIXME: fexp, flog2, flog10 needs to be custom lowered.
198+
getActionDefinitionsBuilder({G_FPOW, G_FEXP, G_FEXP2,
199+
G_FLOG, G_FLOG2, G_FLOG10})
200+
.legalFor({S32})
201+
.scalarize(0);
202202

203203
setAction({G_CTLZ, S32}, Legal);
204204
setAction({G_CTLZ_ZERO_UNDEF, S32}, Legal);

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,54 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
3+
4+
---
5+
name: test_fexp_s32
6+
body: |
7+
bb.0:
8+
liveins: $vgpr0
9+
10+
; CHECK-LABEL: name: test_fexp_s32
11+
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
12+
; CHECK: [[FEXP_:%[0-9]+]]:_(s32) = G_FEXP [[COPY]]
13+
; CHECK: $vgpr0 = COPY [[FEXP_]](s32)
14+
%0:_(s32) = COPY $vgpr0
15+
%1:_(s32) = G_FEXP %0
16+
$vgpr0 = COPY %1
17+
...
18+
19+
---
20+
name: test_fexp_v2s32
21+
body: |
22+
bb.0:
23+
liveins: $vgpr0_vgpr1
24+
25+
; CHECK-LABEL: name: test_fexp_v2s32
26+
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
27+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
28+
; CHECK: [[FEXP_:%[0-9]+]]:_(s32) = G_FEXP [[UV]]
29+
; CHECK: [[FEXP_1:%[0-9]+]]:_(s32) = G_FEXP [[UV1]]
30+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FEXP_]](s32), [[FEXP_1]](s32)
31+
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
32+
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
33+
%1:_(<2 x s32>) = G_FEXP %0
34+
$vgpr0_vgpr1 = COPY %1
35+
...
36+
37+
---
38+
name: test_fexp_v3s32
39+
body: |
40+
bb.0:
41+
liveins: $vgpr0_vgpr1_vgpr2
42+
43+
; CHECK-LABEL: name: test_fexp_v3s32
44+
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
45+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
46+
; CHECK: [[FEXP_:%[0-9]+]]:_(s32) = G_FEXP [[UV]]
47+
; CHECK: [[FEXP_1:%[0-9]+]]:_(s32) = G_FEXP [[UV1]]
48+
; CHECK: [[FEXP_2:%[0-9]+]]:_(s32) = G_FEXP [[UV2]]
49+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FEXP_]](s32), [[FEXP_1]](s32), [[FEXP_2]](s32)
50+
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
51+
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
52+
%1:_(<3 x s32>) = G_FEXP %0
53+
$vgpr0_vgpr1_vgpr2 = COPY %1
54+
...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,54 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
3+
4+
---
5+
name: test_fexp2_s32
6+
body: |
7+
bb.0:
8+
liveins: $vgpr0
9+
10+
; CHECK-LABEL: name: test_fexp2_s32
11+
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
12+
; CHECK: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[COPY]]
13+
; CHECK: $vgpr0 = COPY [[FEXP2_]](s32)
14+
%0:_(s32) = COPY $vgpr0
15+
%1:_(s32) = G_FEXP2 %0
16+
$vgpr0 = COPY %1
17+
...
18+
19+
---
20+
name: test_fexp2_v2s32
21+
body: |
22+
bb.0:
23+
liveins: $vgpr0_vgpr1
24+
25+
; CHECK-LABEL: name: test_fexp2_v2s32
26+
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
27+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
28+
; CHECK: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[UV]]
29+
; CHECK: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[UV1]]
30+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FEXP2_]](s32), [[FEXP2_1]](s32)
31+
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
32+
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
33+
%1:_(<2 x s32>) = G_FEXP2 %0
34+
$vgpr0_vgpr1 = COPY %1
35+
...
36+
37+
---
38+
name: test_fexp2_v3s32
39+
body: |
40+
bb.0:
41+
liveins: $vgpr0_vgpr1_vgpr2
42+
43+
; CHECK-LABEL: name: test_fexp2_v3s32
44+
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
45+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
46+
; CHECK: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[UV]]
47+
; CHECK: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[UV1]]
48+
; CHECK: [[FEXP2_2:%[0-9]+]]:_(s32) = G_FEXP2 [[UV2]]
49+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FEXP2_]](s32), [[FEXP2_1]](s32), [[FEXP2_2]](s32)
50+
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
51+
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
52+
%1:_(<3 x s32>) = G_FEXP2 %0
53+
$vgpr0_vgpr1_vgpr2 = COPY %1
54+
...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,54 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
3+
4+
---
5+
name: test_flog_s32
6+
body: |
7+
bb.0:
8+
liveins: $vgpr0
9+
10+
; CHECK-LABEL: name: test_flog_s32
11+
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
12+
; CHECK: [[FLOG:%[0-9]+]]:_(s32) = G_FLOG [[COPY]]
13+
; CHECK: $vgpr0 = COPY [[FLOG]](s32)
14+
%0:_(s32) = COPY $vgpr0
15+
%1:_(s32) = G_FLOG %0
16+
$vgpr0 = COPY %1
17+
...
18+
19+
---
20+
name: test_flog_v2s32
21+
body: |
22+
bb.0:
23+
liveins: $vgpr0_vgpr1
24+
25+
; CHECK-LABEL: name: test_flog_v2s32
26+
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
27+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
28+
; CHECK: [[FLOG:%[0-9]+]]:_(s32) = G_FLOG [[UV]]
29+
; CHECK: [[FLOG1:%[0-9]+]]:_(s32) = G_FLOG [[UV1]]
30+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FLOG]](s32), [[FLOG1]](s32)
31+
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
32+
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
33+
%1:_(<2 x s32>) = G_FLOG %0
34+
$vgpr0_vgpr1 = COPY %1
35+
...
36+
37+
---
38+
name: test_flog_v3s32
39+
body: |
40+
bb.0:
41+
liveins: $vgpr0_vgpr1_vgpr2
42+
43+
; CHECK-LABEL: name: test_flog_v3s32
44+
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
45+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
46+
; CHECK: [[FLOG:%[0-9]+]]:_(s32) = G_FLOG [[UV]]
47+
; CHECK: [[FLOG1:%[0-9]+]]:_(s32) = G_FLOG [[UV1]]
48+
; CHECK: [[FLOG2:%[0-9]+]]:_(s32) = G_FLOG [[UV2]]
49+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FLOG]](s32), [[FLOG1]](s32), [[FLOG2]](s32)
50+
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
51+
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
52+
%1:_(<3 x s32>) = G_FLOG %0
53+
$vgpr0_vgpr1_vgpr2 = COPY %1
54+
...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,54 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
3+
4+
---
5+
name: test_flog10_s32
6+
body: |
7+
bb.0:
8+
liveins: $vgpr0
9+
10+
; CHECK-LABEL: name: test_flog10_s32
11+
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
12+
; CHECK: [[FLOG10_:%[0-9]+]]:_(s32) = G_FLOG10 [[COPY]]
13+
; CHECK: $vgpr0 = COPY [[FLOG10_]](s32)
14+
%0:_(s32) = COPY $vgpr0
15+
%1:_(s32) = G_FLOG10 %0
16+
$vgpr0 = COPY %1
17+
...
18+
19+
---
20+
name: test_flog10_v2s32
21+
body: |
22+
bb.0:
23+
liveins: $vgpr0_vgpr1
24+
25+
; CHECK-LABEL: name: test_flog10_v2s32
26+
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
27+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
28+
; CHECK: [[FLOG10_:%[0-9]+]]:_(s32) = G_FLOG10 [[UV]]
29+
; CHECK: [[FLOG10_1:%[0-9]+]]:_(s32) = G_FLOG10 [[UV1]]
30+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FLOG10_]](s32), [[FLOG10_1]](s32)
31+
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
32+
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
33+
%1:_(<2 x s32>) = G_FLOG10 %0
34+
$vgpr0_vgpr1 = COPY %1
35+
...
36+
37+
---
38+
name: test_flog10_v3s32
39+
body: |
40+
bb.0:
41+
liveins: $vgpr0_vgpr1_vgpr2
42+
43+
; CHECK-LABEL: name: test_flog10_v3s32
44+
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
45+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
46+
; CHECK: [[FLOG10_:%[0-9]+]]:_(s32) = G_FLOG10 [[UV]]
47+
; CHECK: [[FLOG10_1:%[0-9]+]]:_(s32) = G_FLOG10 [[UV1]]
48+
; CHECK: [[FLOG10_2:%[0-9]+]]:_(s32) = G_FLOG10 [[UV2]]
49+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FLOG10_]](s32), [[FLOG10_1]](s32), [[FLOG10_2]](s32)
50+
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
51+
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
52+
%1:_(<3 x s32>) = G_FLOG10 %0
53+
$vgpr0_vgpr1_vgpr2 = COPY %1
54+
...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,54 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
3+
4+
---
5+
name: test_flog2_s32
6+
body: |
7+
bb.0:
8+
liveins: $vgpr0
9+
10+
; CHECK-LABEL: name: test_flog2_s32
11+
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
12+
; CHECK: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[COPY]]
13+
; CHECK: $vgpr0 = COPY [[FLOG2_]](s32)
14+
%0:_(s32) = COPY $vgpr0
15+
%1:_(s32) = G_FLOG2 %0
16+
$vgpr0 = COPY %1
17+
...
18+
19+
---
20+
name: test_flog2_v2s32
21+
body: |
22+
bb.0:
23+
liveins: $vgpr0_vgpr1
24+
25+
; CHECK-LABEL: name: test_flog2_v2s32
26+
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
27+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
28+
; CHECK: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]]
29+
; CHECK: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]]
30+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FLOG2_]](s32), [[FLOG2_1]](s32)
31+
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
32+
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
33+
%1:_(<2 x s32>) = G_FLOG2 %0
34+
$vgpr0_vgpr1 = COPY %1
35+
...
36+
37+
---
38+
name: test_flog2_v3s32
39+
body: |
40+
bb.0:
41+
liveins: $vgpr0_vgpr1_vgpr2
42+
43+
; CHECK-LABEL: name: test_flog2_v3s32
44+
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
45+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
46+
; CHECK: [[FLOG2_:%[0-9]+]]:_(s32) = G_FLOG2 [[UV]]
47+
; CHECK: [[FLOG2_1:%[0-9]+]]:_(s32) = G_FLOG2 [[UV1]]
48+
; CHECK: [[FLOG2_2:%[0-9]+]]:_(s32) = G_FLOG2 [[UV2]]
49+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FLOG2_]](s32), [[FLOG2_1]](s32), [[FLOG2_2]](s32)
50+
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
51+
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
52+
%1:_(<3 x s32>) = G_FLOG2 %0
53+
$vgpr0_vgpr1_vgpr2 = COPY %1
54+
...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,62 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
3+
4+
---
5+
name: test_fpow_s32
6+
body: |
7+
bb.0:
8+
liveins: $vgpr0, $vgpr1
9+
10+
; CHECK-LABEL: name: test_fpow_s32
11+
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
12+
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
13+
; CHECK: [[FPOW:%[0-9]+]]:_(s32) = G_FPOW [[COPY]], [[COPY1]]
14+
; CHECK: $vgpr0 = COPY [[FPOW]](s32)
15+
%0:_(s32) = COPY $vgpr0
16+
%1:_(s32) = COPY $vgpr1
17+
%2:_(s32) = G_FPOW %0, %1
18+
$vgpr0 = COPY %2
19+
...
20+
21+
---
22+
name: test_fpow_v2s32
23+
body: |
24+
bb.0.entry:
25+
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
26+
27+
; CHECK-LABEL: name: test_fpow_v2s32
28+
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
29+
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
30+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
31+
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
32+
; CHECK: [[FPOW:%[0-9]+]]:_(s32) = G_FPOW [[UV]], [[UV2]]
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; CHECK: [[FPOW1:%[0-9]+]]:_(s32) = G_FPOW [[UV1]], [[UV3]]
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPOW]](s32), [[FPOW1]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
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%2:_(<2 x s32>) = G_FPOW %0, %1
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$vgpr0_vgpr1 = COPY %2
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...
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---
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name: test_fpow_v3s32
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body: |
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bb.0.entry:
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liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
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; CHECK-LABEL: name: test_fpow_v3s32
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; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
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; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
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; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
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; CHECK: [[FPOW:%[0-9]+]]:_(s32) = G_FPOW [[UV]], [[UV3]]
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; CHECK: [[FPOW1:%[0-9]+]]:_(s32) = G_FPOW [[UV1]], [[UV4]]
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; CHECK: [[FPOW2:%[0-9]+]]:_(s32) = G_FPOW [[UV2]], [[UV5]]
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FPOW]](s32), [[FPOW1]](s32), [[FPOW2]](s32)
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; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
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%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
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%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
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%2:_(<3 x s32>) = G_FPOW %0, %1
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$vgpr0_vgpr1_vgpr2 = COPY %2
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...

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