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Reland "[X86] Support -march=diamondrapids (#113881)" (#116564)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
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‎clang/docs/ReleaseNotes.rst

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -769,6 +769,8 @@ X86 Support
769769
- Support ISA of ``AMX-TF32``.
770770
- Support ISA of ``MOVRS``.
771771

772+
- Supported ``-march/tune=diamondrapids``
773+
772774
Arm and AArch64 Support
773775
^^^^^^^^^^^^^^^^^^^^^^^
774776

‎clang/lib/Basic/Targets/X86.cpp

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Original file line numberDiff line numberDiff line change
@@ -667,6 +667,7 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
667667
case CK_GraniterapidsD:
668668
case CK_Emeraldrapids:
669669
case CK_Clearwaterforest:
670+
case CK_Diamondrapids:
670671
// FIXME: Historically, we defined this legacy name, it would be nice to
671672
// remove it at some point. We've never exposed fine-grained names for
672673
// recent primary x86 CPUs, and we should keep it that way.
@@ -1651,6 +1652,7 @@ std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
16511652
case CK_GraniterapidsD:
16521653
case CK_Emeraldrapids:
16531654
case CK_Clearwaterforest:
1655+
case CK_Diamondrapids:
16541656
case CK_KNL:
16551657
case CK_KNM:
16561658
// K7

‎clang/test/CodeGen/attr-cpuspecific-cpus.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,7 @@ ATTR(cpu_specific(icelake_client)) void CPU(void){}
4343
ATTR(cpu_specific(tigerlake)) void CPU(void){}
4444
ATTR(cpu_specific(alderlake)) void CPU(void){}
4545
ATTR(cpu_specific(sapphirerapids)) void CPU(void){}
46+
ATTR(cpu_specific(diamondrapids)) void CPU(void){}
4647

4748
// ALIAS CPUs
4849
ATTR(cpu_specific(pentium_iii_no_xmm_regs)) void CPU0(void){}

‎clang/test/CodeGen/attr-target-mv.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@ int __attribute__((target("arch=lunarlake"))) foo(void) {return 23;}
2929
int __attribute__((target("arch=gracemont"))) foo(void) {return 24;}
3030
int __attribute__((target("arch=pantherlake"))) foo(void) {return 25;}
3131
int __attribute__((target("arch=clearwaterforest"))) foo(void) {return 26;}
32+
int __attribute__((target("arch=diamondrapids"))) foo(void) {return 27;}
3233
int __attribute__((target("default"))) foo(void) { return 2; }
3334

3435
int bar(void) {

‎clang/test/CodeGen/target-builtin-noerror.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -209,4 +209,5 @@ void verifycpustrings(void) {
209209
(void)__builtin_cpu_is("znver3");
210210
(void)__builtin_cpu_is("znver4");
211211
(void)__builtin_cpu_is("znver5");
212+
(void)__builtin_cpu_is("diamondrapids");
212213
}

‎clang/test/Driver/x86-march.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -120,6 +120,10 @@
120120
// RUN: | FileCheck %s -check-prefix=clearwaterforest
121121
// clearwaterforest: "-target-cpu" "clearwaterforest"
122122
//
123+
// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=diamondrapids 2>&1 \
124+
// RUN: | FileCheck %s -check-prefix=diamondrapids
125+
// diamondrapids: "-target-cpu" "diamondrapids"
126+
//
123127
// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=lakemont 2>&1 \
124128
// RUN: | FileCheck %s -check-prefix=lakemont
125129
// lakemont: "-target-cpu" "lakemont"

‎clang/test/Misc/target-invalid-cpu-note/x86.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -69,6 +69,7 @@
6969
// X86-SAME: {{^}}, graniterapids-d
7070
// X86-SAME: {{^}}, emeraldrapids
7171
// X86-SAME: {{^}}, clearwaterforest
72+
// X86-SAME: {{^}}, diamondrapids
7273
// X86-SAME: {{^}}, knl
7374
// X86-SAME: {{^}}, knm
7475
// X86-SAME: {{^}}, lakemont
@@ -155,6 +156,7 @@
155156
// X86_64-SAME: {{^}}, graniterapids-d
156157
// X86_64-SAME: {{^}}, emeraldrapids
157158
// X86_64-SAME: {{^}}, clearwaterforest
159+
// X86_64-SAME: {{^}}, diamondrapids
158160
// X86_64-SAME: {{^}}, knl
159161
// X86_64-SAME: {{^}}, knm
160162
// X86_64-SAME: {{^}}, k8
@@ -250,6 +252,7 @@
250252
// TUNE_X86-SAME: {{^}}, graniterapids-d
251253
// TUNE_X86-SAME: {{^}}, emeraldrapids
252254
// TUNE_X86-SAME: {{^}}, clearwaterforest
255+
// TUNE_X86-SAME: {{^}}, diamondrapids
253256
// TUNE_X86-SAME: {{^}}, knl
254257
// TUNE_X86-SAME: {{^}}, knm
255258
// TUNE_X86-SAME: {{^}}, lakemont
@@ -352,6 +355,7 @@
352355
// TUNE_X86_64-SAME: {{^}}, graniterapids-d
353356
// TUNE_X86_64-SAME: {{^}}, emeraldrapids
354357
// TUNE_X86_64-SAME: {{^}}, clearwaterforest
358+
// TUNE_X86_64-SAME: {{^}}, diamondrapids
355359
// TUNE_X86_64-SAME: {{^}}, knl
356360
// TUNE_X86_64-SAME: {{^}}, knm
357361
// TUNE_X86_64-SAME: {{^}}, lakemont

‎clang/test/Preprocessor/predefined-arch-macros.c

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1867,13 +1867,23 @@
18671867
// RUN: %clang -march=graniterapids-d -m32 -E -dM %s -o - 2>&1 \
18681868
// RUN: --target=i386 \
18691869
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_GNR_M32,CHECK_GNRD_M32
1870+
// RUN: %clang -march=diamondrapids -m32 -E -dM %s -o - 2>&1 \
1871+
// RUN: --target=i386 \
1872+
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_GNR_M32,CHECK_GNRD_M32,CHECK_DMR_M32
18701873
// CHECK_GNR_M32: #define __AES__ 1
1874+
// CHECK_DMR_M32: #define __AMX_AVX512__ 1
18711875
// CHECK_GNR_M32: #define __AMX_BF16__ 1
18721876
// CHECK_GNR_M32-NOT: #define __AMX_COMPLEX__ 1
18731877
// CHECK_GNRD_M32: #define __AMX_COMPLEX__ 1
18741878
// CHECK_GNR_M32: #define __AMX_FP16__ 1
1879+
// CHECK_DMR_M32: #define __AMX_FP8__ 1
18751880
// CHECK_GNR_M32: #define __AMX_INT8__ 1
1881+
// CHECK_DMR_M32: #define __AMX_MOVRS__ 1
1882+
// CHECK_DMR_M32: #define __AMX_TF32__ 1
18761883
// CHECK_GNR_M32: #define __AMX_TILE__ 1
1884+
// CHECK_DMR_M32: #define __AMX_TRANSPOSE__ 1
1885+
// CHECK_DMR_M32: #define __AVX10_2_512__ 1
1886+
// CHECK_DMR_M32: #define __AVX10_2__ 1
18771887
// CHECK_GNR_M32: #define __AVX2__ 1
18781888
// CHECK_GNR_M32: #define __AVX512BF16__ 1
18791889
// CHECK_GNR_M32: #define __AVX512BITALG__ 1
@@ -1888,13 +1898,21 @@
18881898
// CHECK_GNR_M32: #define __AVX512VL__ 1
18891899
// CHECK_GNR_M32: #define __AVX512VNNI__ 1
18901900
// CHECK_GNR_M32: #define __AVX512VPOPCNTDQ__ 1
1901+
// CHECK_DMR_M32: #define __AVXIFMA__ 1
1902+
// CHECK_DMR_M32: #define __AVXNECONVERT__ 1
1903+
// CHECK_DMR_M32: #define __AVXVNNIINT16__ 1
1904+
// CHECK_DMR_M32: #define __AVXVNNIINT8__ 1
18911905
// CHECK_GNR_M32: #define __AVXVNNI__ 1
18921906
// CHECK_GNR_M32: #define __AVX__ 1
18931907
// CHECK_GNR_M32: #define __BMI2__ 1
18941908
// CHECK_GNR_M32: #define __BMI__ 1
1909+
// CHECK_DMR_M32: #define __CCMP__ 1
1910+
// CHECK_DMR_M32: #define __CF__ 1
18951911
// CHECK_GNR_M32: #define __CLDEMOTE__ 1
18961912
// CHECK_GNR_M32: #define __CLFLUSHOPT__ 1
18971913
// CHECK_GNR_M32: #define __CLWB__ 1
1914+
// CHECK_DMR_M32: #define __CMPCCXADD__ 1
1915+
// CHECK_DMR_M32: #define __EGPR__ 1
18981916
// CHECK_GNR_M32: #define __ENQCMD__ 1
18991917
// CHECK_GNR_M32: #define __EVEX256__ 1
19001918
// CHECK_GNR_M32: #define __EVEX512__ 1
@@ -1905,20 +1923,28 @@
19051923
// CHECK_GNR_M32: #define __LZCNT__ 1
19061924
// CHECK_GNR_M32: #define __MMX__ 1
19071925
// CHECK_GNR_M32: #define __MOVBE__ 1
1926+
// CHECK_DMR_M32: #define __MOVRS__ 1
1927+
// CHECK_DMR_M32: #define __NDD__ 1
1928+
// CHECK_DMR_M32: #define __NF__ 1
19081929
// CHECK_GNR_M32: #define __PCLMUL__ 1
19091930
// CHECK_GNR_M32: #define __PCONFIG__ 1
19101931
// CHECK_GNR_M32: #define __PKU__ 1
19111932
// CHECK_GNR_M32: #define __POPCNT__ 1
1933+
// CHECK_DMR_M32: #define __PPX__ 1
19121934
// CHECK_GNR_M32: #define __PREFETCHI__ 1
19131935
// CHECK_GNR_M32: #define __PRFCHW__ 1
19141936
// CHECK_GNR_M32: #define __PTWRITE__ 1
1937+
// CHECK_DMR_M32: #define __PUSH2POP2__ 1
19151938
// CHECK_GNR_M32: #define __RDPID__ 1
19161939
// CHECK_GNR_M32: #define __RDRND__ 1
19171940
// CHECK_GNR_M32: #define __RDSEED__ 1
19181941
// CHECK_GNR_M32: #define __SERIALIZE__ 1
19191942
// CHECK_GNR_M32: #define __SGX__ 1
1943+
// CHECK_DMR_M32: #define __SHA512__ 1
19201944
// CHECK_GNR_M32: #define __SHA__ 1
19211945
// CHECK_GNR_M32: #define __SHSTK__ 1
1946+
// CHECK_DMR_M32: #define __SM3__ 1
1947+
// CHECK_DMR_M32: #define __SM4__ 1
19221948
// CHECK_GNR_M32: #define __SSE2__ 1
19231949
// CHECK_GNR_M32: #define __SSE3__ 1
19241950
// CHECK_GNR_M32: #define __SSE4_1__ 1
@@ -1935,6 +1961,7 @@
19351961
// CHECK_GNR_M32: #define __XSAVEOPT__ 1
19361962
// CHECK_GNR_M32: #define __XSAVES__ 1
19371963
// CHECK_GNR_M32: #define __XSAVE__ 1
1964+
// CHECK_DMR_M32: #define __ZU__ 1
19381965
// CHECK_GNR_M32: #define __corei7 1
19391966
// CHECK_GNR_M32: #define __corei7__ 1
19401967
// CHECK_GNR_M32: #define __i386 1
@@ -1948,13 +1975,23 @@
19481975
// RUN: %clang -march=graniterapids-d -m64 -E -dM %s -o - 2>&1 \
19491976
// RUN: --target=x86_64 \
19501977
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_GNR_M64,CHECK_GNRD_M64
1978+
// RUN: %clang -march=diamondrapids -m64 -E -dM %s -o - 2>&1 \
1979+
// RUN: --target=x86_64 \
1980+
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_GNR_M64,CHECK_GNRD_M64,CHECK_DMR_M64
19511981
// CHECK_GNR_M64: #define __AES__ 1
1982+
// CHECK_DMR_M64: #define __AMX_AVX512__ 1
19521983
// CHECK_GNR_M64: #define __AMX_BF16__ 1
19531984
// CHECK_GNR_M64-NOT: #define __AMX_COMPLEX__ 1
19541985
// CHECK_GNRD_M64: #define __AMX_COMPLEX__ 1
19551986
// CHECK_GNR_M64: #define __AMX_FP16__ 1
1987+
// CHECK_DMR_M64: #define __AMX_FP8__ 1
19561988
// CHECK_GNR_M64: #define __AMX_INT8__ 1
1989+
// CHECK_DMR_M64: #define __AMX_MOVRS__ 1
1990+
// CHECK_DMR_M64: #define __AMX_TF32__ 1
19571991
// CHECK_GNR_M64: #define __AMX_TILE__ 1
1992+
// CHECK_DMR_M64: #define __AMX_TRANSPOSE__ 1
1993+
// CHECK_DMR_M64: #define __AVX10_2_512__ 1
1994+
// CHECK_DMR_M64: #define __AVX10_2__ 1
19581995
// CHECK_GNR_M64: #define __AVX2__ 1
19591996
// CHECK_GNR_M64: #define __AVX512BF16__ 1
19601997
// CHECK_GNR_M64: #define __AVX512BITALG__ 1
@@ -1969,13 +2006,21 @@
19692006
// CHECK_GNR_M64: #define __AVX512VL__ 1
19702007
// CHECK_GNR_M64: #define __AVX512VNNI__ 1
19712008
// CHECK_GNR_M64: #define __AVX512VPOPCNTDQ__ 1
2009+
// CHECK_DMR_M64: #define __AVXIFMA__ 1
2010+
// CHECK_DMR_M64: #define __AVXNECONVERT__ 1
2011+
// CHECK_DMR_M64: #define __AVXVNNIINT16__ 1
2012+
// CHECK_DMR_M64: #define __AVXVNNIINT8__ 1
19722013
// CHECK_GNR_M64: #define __AVXVNNI__ 1
19732014
// CHECK_GNR_M64: #define __AVX__ 1
19742015
// CHECK_GNR_M64: #define __BMI2__ 1
19752016
// CHECK_GNR_M64: #define __BMI__ 1
2017+
// CHECK_DMR_M64: #define __CCMP__ 1
2018+
// CHECK_DMR_M64: #define __CF__ 1
19762019
// CHECK_GNR_M64: #define __CLDEMOTE__ 1
19772020
// CHECK_GNR_M64: #define __CLFLUSHOPT__ 1
19782021
// CHECK_GNR_M64: #define __CLWB__ 1
2022+
// CHECK_DMR_M64: #define __CMPCCXADD__ 1
2023+
// CHECK_DMR_M64: #define __EGPR__ 1
19792024
// CHECK_GNR_M64: #define __ENQCMD__ 1
19802025
// CHECK_GNR_M64: #define __EVEX256__ 1
19812026
// CHECK_GNR_M64: #define __EVEX512__ 1
@@ -1986,20 +2031,28 @@
19862031
// CHECK_GNR_M64: #define __LZCNT__ 1
19872032
// CHECK_GNR_M64: #define __MMX__ 1
19882033
// CHECK_GNR_M64: #define __MOVBE__ 1
2034+
// CHECK_DMR_M64: #define __MOVRS__ 1
2035+
// CHECK_DMR_M64: #define __NDD__ 1
2036+
// CHECK_DMR_M64: #define __NF__ 1
19892037
// CHECK_GNR_M64: #define __PCLMUL__ 1
19902038
// CHECK_GNR_M64: #define __PCONFIG__ 1
19912039
// CHECK_GNR_M64: #define __PKU__ 1
19922040
// CHECK_GNR_M64: #define __POPCNT__ 1
2041+
// CHECK_DMR_M64: #define __PPX__ 1
19932042
// CHECK_GNR_M64: #define __PREFETCHI__ 1
19942043
// CHECK_GNR_M64: #define __PRFCHW__ 1
19952044
// CHECK_GNR_M64: #define __PTWRITE__ 1
2045+
// CHECK_DMR_M64: #define __PUSH2POP2__ 1
19962046
// CHECK_GNR_M64: #define __RDPID__ 1
19972047
// CHECK_GNR_M64: #define __RDRND__ 1
19982048
// CHECK_GNR_M64: #define __RDSEED__ 1
19992049
// CHECK_GNR_M64: #define __SERIALIZE__ 1
20002050
// CHECK_GNR_M64: #define __SGX__ 1
2051+
// CHECK_DMR_M64: #define __SHA512__ 1
20012052
// CHECK_GNR_M64: #define __SHA__ 1
20022053
// CHECK_GNR_M64: #define __SHSTK__ 1
2054+
// CHECK_DMR_M64: #define __SM3__ 1
2055+
// CHECK_DMR_M64: #define __SM4__ 1
20032056
// CHECK_GNR_M64: #define __SSE2__ 1
20042057
// CHECK_GNR_M64: #define __SSE3__ 1
20052058
// CHECK_GNR_M64: #define __SSE4_1__ 1
@@ -2016,6 +2069,7 @@
20162069
// CHECK_GNR_M64: #define __XSAVEOPT__ 1
20172070
// CHECK_GNR_M64: #define __XSAVES__ 1
20182071
// CHECK_GNR_M64: #define __XSAVE__ 1
2072+
// CHECK_DMR_M64: #define __ZU__ 1
20192073
// CHECK_GNR_M64: #define __amd64 1
20202074
// CHECK_GNR_M64: #define __amd64__ 1
20212075
// CHECK_GNR_M64: #define __corei7 1

‎compiler-rt/lib/builtins/cpu_model/x86.c

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -103,6 +103,7 @@ enum ProcessorSubtypes {
103103
INTEL_COREI7_ARROWLAKE_S,
104104
INTEL_COREI7_PANTHERLAKE,
105105
AMDFAM1AH_ZNVER5,
106+
INTEL_COREI7_DIAMONDRAPIDS,
106107
CPU_SUBTYPE_MAX
107108
};
108109

@@ -600,6 +601,19 @@ static const char *getIntelProcessorTypeAndSubtype(unsigned Family,
600601
break;
601602
}
602603
break;
604+
case 19:
605+
switch (Model) {
606+
// Diamond Rapids:
607+
case 0x01:
608+
CPU = "diamondrapids";
609+
*Type = INTEL_COREI7;
610+
*Subtype = INTEL_COREI7_DIAMONDRAPIDS;
611+
break;
612+
613+
default: // Unknown family 19 CPU.
614+
break;
615+
}
616+
break;
603617
default:
604618
break; // Unknown.
605619
}

‎llvm/docs/ReleaseNotes.md

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -237,6 +237,8 @@ Changes to the X86 Backend
237237

238238
* Supported ISA of `MSR_IMM`.
239239

240+
* Supported ``-mcpu=diamondrapids``
241+
240242
Changes to the OCaml bindings
241243
-----------------------------
242244

‎llvm/include/llvm/TargetParser/X86TargetParser.def

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -107,6 +107,7 @@ X86_CPU_SUBTYPE(INTEL_COREI7_ARROWLAKE, "arrowlake")
107107
X86_CPU_SUBTYPE(INTEL_COREI7_ARROWLAKE_S, "arrowlake-s")
108108
X86_CPU_SUBTYPE(INTEL_COREI7_PANTHERLAKE, "pantherlake")
109109
X86_CPU_SUBTYPE(AMDFAM1AH_ZNVER5, "znver5")
110+
X86_CPU_SUBTYPE(INTEL_COREI7_DIAMONDRAPIDS, "diamondrapids")
110111

111112
// Alternate names supported by __builtin_cpu_is and target multiversioning.
112113
X86_CPU_SUBTYPE_ALIAS(INTEL_COREI7_ALDERLAKE, "raptorlake")

‎llvm/include/llvm/TargetParser/X86TargetParser.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -121,6 +121,7 @@ enum CPUKind {
121121
CK_GraniterapidsD,
122122
CK_Emeraldrapids,
123123
CK_Clearwaterforest,
124+
CK_Diamondrapids,
124125
CK_KNL,
125126
CK_KNM,
126127
CK_Lakemont,

‎llvm/lib/Target/X86/X86.td

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1155,6 +1155,33 @@ def ProcessorFeatures {
11551155
list<SubtargetFeature> GNRDFeatures =
11561156
!listconcat(GNRFeatures, GNRDAdditionalFeatures);
11571157

1158+
// Diamond Rapids
1159+
list<SubtargetFeature> DMRAdditionalFeatures = [FeatureAVX10_2_512,
1160+
FeatureSM4,
1161+
FeatureCMPCCXADD,
1162+
FeatureAVXIFMA,
1163+
FeatureAVXNECONVERT,
1164+
FeatureAVXVNNIINT8,
1165+
FeatureAVXVNNIINT16,
1166+
FeatureSHA512,
1167+
FeatureSM3,
1168+
FeatureEGPR,
1169+
FeatureZU,
1170+
FeatureCCMP,
1171+
FeaturePush2Pop2,
1172+
FeaturePPX,
1173+
FeatureNDD,
1174+
FeatureNF,
1175+
FeatureCF,
1176+
FeatureMOVRS,
1177+
FeatureAMXMOVRS,
1178+
FeatureAMXAVX512,
1179+
FeatureAMXFP8,
1180+
FeatureAMXTF32,
1181+
FeatureAMXTRANSPOSE];
1182+
list<SubtargetFeature> DMRFeatures =
1183+
!listconcat(GNRDFeatures, DMRAdditionalFeatures);
1184+
11581185
// Atom
11591186
list<SubtargetFeature> AtomFeatures = [FeatureX87,
11601187
FeatureCX8,
@@ -1856,6 +1883,8 @@ foreach P = ["graniterapids-d", "graniterapids_d"] in {
18561883
def : ProcModel<P, SapphireRapidsModel,
18571884
ProcessorFeatures.GNRDFeatures, ProcessorFeatures.GNRTuning>;
18581885
}
1886+
def : ProcModel<"diamondrapids", SapphireRapidsModel,
1887+
ProcessorFeatures.DMRFeatures, ProcessorFeatures.GNRTuning>;
18591888

18601889
// AMD CPUs.
18611890

‎llvm/lib/TargetParser/Host.cpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1010,6 +1010,19 @@ static StringRef getIntelProcessorTypeAndSubtype(unsigned Family,
10101010
CPU = "pentium4";
10111011
break;
10121012
}
1013+
case 19:
1014+
switch (Model) {
1015+
// Diamond Rapids:
1016+
case 0x01:
1017+
CPU = "diamondrapids";
1018+
*Type = X86::INTEL_COREI7;
1019+
*Subtype = X86::INTEL_COREI7_DIAMONDRAPIDS;
1020+
break;
1021+
1022+
default: // Unknown family 19 CPU.
1023+
break;
1024+
}
1025+
break;
10131026
default:
10141027
break; // Unknown.
10151028
}

‎llvm/lib/TargetParser/X86TargetParser.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -138,6 +138,14 @@ constexpr FeatureBitset FeaturesSapphireRapids =
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FeatureWAITPKG;
139139
constexpr FeatureBitset FeaturesGraniteRapids =
140140
FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
141+
constexpr FeatureBitset FeaturesDiamondRapids =
142+
FeaturesGraniteRapids | FeatureAMX_COMPLEX | FeatureAVX10_2_512 |
143+
FeatureCMPCCXADD | FeatureAVXIFMA | FeatureAVXNECONVERT |
144+
FeatureAVXVNNIINT8 | FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 |
145+
FeatureSM4 | FeatureEGPR | FeatureZU | FeatureCCMP | FeaturePush2Pop2 |
146+
FeaturePPX | FeatureNDD | FeatureNF | FeatureCF | FeatureMOVRS |
147+
FeatureAMX_MOVRS | FeatureAMX_AVX512 | FeatureAMX_FP8 | FeatureAMX_TF32 |
148+
FeatureAMX_TRANSPOSE;
141149

142150
// Intel Atom processors.
143151
// Bonnell has feature parity with Core2 and adds MOVBE.
@@ -381,6 +389,8 @@ constexpr ProcInfo Processors[] = {
381389
{ {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512FP16, FeaturesSapphireRapids, 'n', false },
382390
// Clearwaterforest microarchitecture based processors.
383391
{ {"clearwaterforest"}, CK_Lunarlake, FEATURE_AVX2, FeaturesClearwaterforest, 'p', false },
392+
// Diamond Rapids microarchitecture based processors.
393+
{ {"diamondrapids"}, CK_Diamondrapids, FEATURE_AVX10_2_512, FeaturesDiamondRapids, 'z', false },
384394
// Knights Landing processor.
385395
{ {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', false },
386396
{ {"mic_avx512"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', true },

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