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[AMDGPU] Fix implicit $vcc operands after parsing MIR (#87781)
MIParser checks that implicit operands match the instruction definition, so they have to be $vcc even in wave32 mode. Use the mirFileLoaded hook to fix them after MIParser's checks, converting them to $vcc_lo which is what that rest of CodeGen expects. This is all just extending the fixImplicitOperands hack which was introduced with GFX10, but at least it makes it possible to write a MIR test which creates the same instructions that normal CodeGen would generate.
1 parent 9c66036 commit 9c58f3a

11 files changed

+130
-93
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -642,6 +642,17 @@ void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
642642
Policy.ShouldTrackLaneMasks = true;
643643
}
644644

645+
void GCNSubtarget::mirFileLoaded(MachineFunction &MF) const {
646+
if (isWave32()) {
647+
// Fix implicit $vcc operands after MIParser has verified that they match
648+
// the instruction definitions.
649+
for (auto &MBB : MF) {
650+
for (auto &MI : MBB)
651+
InstrInfo.fixImplicitOperands(MI);
652+
}
653+
}
654+
}
655+
645656
bool GCNSubtarget::hasMadF16() const {
646657
return InstrInfo.pseudoToMCOpcode(AMDGPU::V_MAD_F16_e64) != -1;
647658
}

‎llvm/lib/Target/AMDGPU/GCNSubtarget.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -923,6 +923,8 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
923923
void overrideSchedPolicy(MachineSchedPolicy &Policy,
924924
unsigned NumRegionInstrs) const override;
925925

926+
void mirFileLoaded(MachineFunction &MF) const override;
927+
926928
unsigned getMaxNumUserSGPRs() const {
927929
return AMDGPU::getMaxNumUserSGPRs(*this);
928930
}

‎llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir

Lines changed: 15 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -586,7 +586,7 @@ name: dpp_reg_sequence_both_combined
586586
tracksRegLiveness: true
587587
body: |
588588
bb.0:
589-
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
589+
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo
590590
591591
%0:vreg_64 = COPY $vgpr0_vgpr1
592592
%1:vreg_64 = COPY $vgpr2_vgpr3
@@ -606,12 +606,12 @@ body: |
606606
# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
607607
# GCN: %5:vreg_64 = REG_SEQUENCE undef %3:vgpr_32, %subreg.sub0, %4, %subreg.sub1
608608
# GCN: %6:vgpr_32 = V_ADD_U32_dpp %8, %1.sub0, %2, 1, 15, 15, 1, implicit $exec
609-
# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
609+
# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec
610610
name: dpp_reg_sequence_first_combined
611611
tracksRegLiveness: true
612612
body: |
613613
bb.0:
614-
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
614+
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo
615615
616616
%0:vreg_64 = COPY $vgpr0_vgpr1
617617
%1:vreg_64 = COPY $vgpr2_vgpr3
@@ -636,7 +636,7 @@ name: dpp_reg_sequence_second_combined
636636
tracksRegLiveness: true
637637
body: |
638638
bb.0:
639-
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
639+
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo
640640
641641
%0:vreg_64 = COPY $vgpr0_vgpr1
642642
%1:vreg_64 = COPY $vgpr2_vgpr3
@@ -656,12 +656,12 @@ body: |
656656
# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
657657
# GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1
658658
# GCN: %6:vgpr_32 = V_ADD_U32_e32 %5.sub0, %2, implicit $exec
659-
# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
659+
# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec
660660
name: dpp_reg_sequence_none_combined
661661
tracksRegLiveness: true
662662
body: |
663663
bb.0:
664-
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
664+
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo
665665
666666
%0:vreg_64 = COPY $vgpr0_vgpr1
667667
%1:vreg_64 = COPY $vgpr2_vgpr3
@@ -683,12 +683,12 @@ body: |
683683
# GCN: S_BRANCH %bb.1
684684
# GCN: bb.1:
685685
# GCN: %6:vgpr_32 = V_ADD_U32_e32 %5.sub0, %2, implicit $exec
686-
# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
686+
# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec
687687
name: dpp_reg_sequence_exec_changed
688688
tracksRegLiveness: true
689689
body: |
690690
bb.0:
691-
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
691+
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo
692692
693693
%0:vreg_64 = COPY $vgpr0_vgpr1
694694
%1:vreg_64 = COPY $vgpr2_vgpr3
@@ -699,6 +699,7 @@ body: |
699699
S_BRANCH %bb.1
700700
701701
bb.1:
702+
liveins: $vcc_lo
702703
%6:vgpr_32 = V_ADD_U32_e32 %4.sub0, %5, implicit $exec
703704
%7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec
704705
...
@@ -712,12 +713,12 @@ body: |
712713
# GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1
713714
# GCN: %6:vreg_64 = REG_SEQUENCE %5.sub0, %subreg.sub0, %5.sub1, %subreg.sub1
714715
# GCN: %7:vgpr_32 = V_ADD_U32_e32 %6.sub0, %2, implicit $exec
715-
# GCN: %8:vgpr_32 = V_ADDC_U32_e32 %6.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
716+
# GCN: %8:vgpr_32 = V_ADDC_U32_e32 %6.sub1, %2, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec
716717
name: dpp_reg_sequence_subreg
717718
tracksRegLiveness: true
718719
body: |
719720
bb.0:
720-
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
721+
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo
721722
722723
%0:vreg_64 = COPY $vgpr0_vgpr1
723724
%1:vreg_64 = COPY $vgpr2_vgpr3
@@ -782,6 +783,7 @@ name: dpp64_add64_impdef
782783
tracksRegLiveness: true
783784
body: |
784785
bb.0:
786+
liveins: $vcc_lo
785787
%0:vreg_64 = IMPLICIT_DEF
786788
%1:vreg_64 = IMPLICIT_DEF
787789
%2:vreg_64 = V_MOV_B64_DPP_PSEUDO %1:vreg_64, %0:vreg_64, 1, 15, 15, 1, implicit $exec
@@ -796,6 +798,7 @@ name: dpp64_add64_undef
796798
tracksRegLiveness: true
797799
body: |
798800
bb.0:
801+
liveins: $vcc_lo
799802
%2:vreg_64 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64, undef %0:vreg_64, 1, 15, 15, 1, implicit $exec
800803
%5:vgpr_32 = V_ADD_U32_e32 %2.sub0, undef %4:vgpr_32, implicit $exec
801804
%6:vgpr_32 = V_ADDC_U32_e32 %2.sub1, undef %4, implicit-def $vcc, implicit $vcc, implicit $exec
@@ -860,12 +863,12 @@ body: |
860863

861864
# GCN-LABEL: name: dont_combine_more_than_one_operand_dpp_reg_sequence
862865
# GCN: %5:vgpr_32 = V_ADD_U32_e32 %4.sub0, %4.sub0, implicit $exec
863-
# GCN: %6:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %4.sub1, implicit-def $vcc, implicit $vcc, implicit $exec
866+
# GCN: %6:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %4.sub1, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec
864867
name: dont_combine_more_than_one_operand_dpp_reg_sequence
865868
tracksRegLiveness: true
866869
body: |
867870
bb.0:
868-
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
871+
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo
869872
%0:vreg_64 = COPY $vgpr0_vgpr1
870873
%1:vreg_64 = COPY $vgpr2_vgpr3
871874
%2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec

‎llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -39,19 +39,19 @@ body: |
3939
S_CMP_EQ_U32 %15, undef %15, implicit-def $scc
4040
%19:sreg_32_xm0_xexec = S_CSELECT_B32 -1, 0, implicit killed undef $scc
4141
%20:sreg_32 = IMPLICIT_DEF
42-
dead $vcc_lo = COPY undef %20
42+
$vcc_lo = COPY undef %20
4343
S_CBRANCH_VCCNZ %bb.3, implicit $vcc
4444
S_BRANCH %bb.3
4545
4646
bb.3:
47-
dead $vcc_lo = S_AND_B32 $exec_lo, undef %19, implicit-def dead $scc
47+
$vcc_lo = S_AND_B32 $exec_lo, undef %19, implicit-def dead $scc
4848
S_CBRANCH_VCCNZ %bb.6, implicit $vcc
4949
S_BRANCH %bb.4
5050
5151
bb.4:
5252
%21:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %19, implicit $exec
5353
%22:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, undef %21, implicit $exec
54-
dead $vcc_lo = S_AND_B32 $exec_lo, undef %22, implicit-def dead $scc
54+
$vcc_lo = S_AND_B32 $exec_lo, undef %22, implicit-def dead $scc
5555
S_CBRANCH_VCCNZ %bb.7, implicit $vcc
5656
S_BRANCH %bb.5
5757
@@ -174,7 +174,7 @@ body: |
174174
S_BRANCH %bb.20
175175
176176
bb.28:
177-
dead $vcc_lo = S_AND_B32 $exec_lo, %22, implicit-def dead $scc
177+
$vcc_lo = S_AND_B32 $exec_lo, %22, implicit-def dead $scc
178178
S_CBRANCH_VCCNZ %bb.29, implicit $vcc
179179
S_BRANCH %bb.29
180180

‎llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
# GCN: name: negated_cond_vop2
55
# GCN: %0:sgpr_32 = IMPLICIT_DEF
66
# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
7-
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
7+
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo
88
---
99
name: negated_cond_vop2
1010
body: |
@@ -26,7 +26,7 @@ body: |
2626
# GCN: name: negated_cond_vop3
2727
# GCN: %0:sgpr_32 = IMPLICIT_DEF
2828
# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
29-
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
29+
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo
3030
---
3131
name: negated_cond_vop3
3232
body: |
@@ -48,10 +48,10 @@ body: |
4848
# GCN: name: negated_cond_vop2_redef_vcc1
4949
# GCN: %0:sgpr_32 = IMPLICIT_DEF
5050
# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
51-
# GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
51+
# GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc_lo, implicit $exec
5252
# GCN-NEXT: $vcc_lo = COPY $sgpr0
5353
# GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, $vcc_lo, implicit-def dead $scc
54-
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
54+
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo
5555
---
5656
name: negated_cond_vop2_redef_vcc1
5757
body: |
@@ -77,7 +77,7 @@ body: |
7777
# GCN-NEXT: dead %3:sgpr_32 = V_CMP_NE_U32_e64 %1, 1, implicit $exec
7878
# GCN-NEXT: %2:sgpr_32 = COPY $sgpr0
7979
# GCN-NEXT: $vcc_lo = S_AND_B32 %2, $exec_lo, implicit-def dead $scc
80-
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
80+
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo
8181
---
8282
name: negated_cond_vop3_redef_cmp
8383
body: |
@@ -99,7 +99,7 @@ body: |
9999

100100
# GCN: name: negated_cond_undef_vcc
101101
# GCN: $vcc_lo = S_AND_B32 $exec_lo, undef $vcc_lo, implicit-def dead $scc
102-
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
102+
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo
103103
---
104104
name: negated_cond_undef_vcc
105105
body: |
@@ -118,7 +118,7 @@ body: |
118118
# GCN: name: negated_cond_vop3_imp_vcc
119119
# GCN: $vcc_lo = IMPLICIT_DEF
120120
# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, $vcc_lo, implicit-def dead $scc
121-
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
121+
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo
122122
---
123123
name: negated_cond_vop3_imp_vcc
124124
body: |
@@ -140,7 +140,7 @@ body: |
140140
# GCN: name: negated_cond_vop2_imp_vcc
141141
# GCN: $vcc_lo = IMPLICIT_DEF
142142
# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, $vcc_lo, implicit-def dead $scc
143-
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
143+
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo
144144
---
145145
name: negated_cond_vop2_imp_vcc
146146
body: |
@@ -165,7 +165,7 @@ body: |
165165
# GCN-NEXT: %1:vgpr_32 = COPY $vgpr0
166166
# GCN-NEXT: %2:sgpr_32 = V_CMP_NE_U32_e64 %1, 1, implicit $exec
167167
# GCN-NEXT: $vcc_lo = S_AND_B32 %2, $exec_lo, implicit-def dead $scc
168-
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
168+
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo
169169
---
170170
name: negated_cond_vop3_redef_sel
171171
body: |
@@ -189,7 +189,7 @@ body: |
189189
# GCN: %0:sgpr_32 = IMPLICIT_DEF
190190
# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
191191
# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
192-
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
192+
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo
193193
---
194194
name: negated_cond_vop2_used_sel
195195
body: |
@@ -212,10 +212,10 @@ body: |
212212
# GCN: name: negated_cond_vop2_used_vcc
213213
# GCN: %0:sgpr_32 = IMPLICIT_DEF
214214
# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
215-
# GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
215+
# GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc_lo, implicit $exec
216216
# GCN-NEXT: $sgpr0_sgpr1 = COPY $vcc
217217
# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
218-
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
218+
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo
219219
---
220220
name: negated_cond_vop2_used_vcc
221221
body: |
@@ -241,7 +241,7 @@ body: |
241241
# GCN-NEXT: %1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
242242
# GCN-NEXT: %2:sgpr_32 = V_CMP_NE_U32_e64 %1.sub1, 1, implicit $exec
243243
# GCN-NEXT: $vcc_lo = S_AND_B32 %2, $exec_lo, implicit-def dead $scc
244-
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
244+
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo
245245
---
246246
name: negated_cond_vop3_sel_wrong_subreg1
247247
body: |
@@ -267,7 +267,7 @@ body: |
267267
# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
268268
# GCN-NEXT: %2:sgpr_32 = V_CMP_NE_U32_e64 %1.sub1, 1, implicit $exec
269269
# GCN-NEXT: $vcc_lo = S_AND_B32 %2, $exec_lo, implicit-def dead $scc
270-
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
270+
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo
271271
---
272272
name: negated_cond_vop3_sel_wrong_subreg2
273273
body: |
@@ -291,7 +291,7 @@ body: |
291291
# GCN: %0:sgpr_32 = IMPLICIT_DEF
292292
# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
293293
# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
294-
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
294+
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo
295295
---
296296
name: negated_cond_vop3_sel_right_subreg1
297297
body: |
@@ -315,7 +315,7 @@ body: |
315315
# GCN: %0:sgpr_32 = IMPLICIT_DEF
316316
# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
317317
# GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
318-
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
318+
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo
319319
---
320320
name: negated_cond_vop3_sel_right_subreg2
321321
body: |
@@ -341,7 +341,7 @@ body: |
341341
# GCN-NEXT: %1.sub2_sub3:vreg_128 = IMPLICIT_DEF
342342
# GCN-NEXT: %2:sgpr_32 = V_CMP_NE_U32_e64 %1.sub2, 1, implicit $exec
343343
# GCN-NEXT: $vcc_lo = S_AND_B32 %2, $exec_lo, implicit-def dead $scc
344-
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
344+
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo
345345
---
346346
name: negated_cond_vop3_sel_subreg_overlap
347347
body: |

‎llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,7 @@ body: |
118118
; GCN-NEXT: successors: %bb.2(0x80000000)
119119
; GCN-NEXT: liveins: $vgpr2, $vgpr3, $vgpr4, $vgpr5
120120
; GCN-NEXT: {{ $}}
121-
; GCN-NEXT: KILL implicit-def $vcc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr32_sgpr33_sgpr34_sgpr35_sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63, implicit-def $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99_sgpr100_sgpr101_sgpr102_sgpr103
121+
; GCN-NEXT: KILL implicit-def $vcc_lo, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr32_sgpr33_sgpr34_sgpr35_sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63, implicit-def $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99_sgpr100_sgpr101_sgpr102_sgpr103
122122
; GCN-NEXT: {{ $}}
123123
; GCN-NEXT: bb.2:
124124
; GCN-NEXT: successors: %bb.3(0x80000000)

‎llvm/test/CodeGen/AMDGPU/si-lower-i1-copies-order-of-phi-incomings.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ body: |
6868
; GCN-NEXT: [[PHI4:%[0-9]+]]:sreg_32 = PHI [[S_OR_B32_]], %bb.1, [[S_OR_B32_1]], %bb.2
6969
; GCN-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
7070
; GCN-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 4
71-
; GCN-NEXT: [[V_ADD_U:%[0-9]+]]:vreg_64 = V_ADD_U64_PSEUDO [[PHI3]], killed [[S_MOV_B64_]], implicit-def dead $vcc, implicit $exec
71+
; GCN-NEXT: [[V_ADD_U:%[0-9]+]]:vreg_64 = V_ADD_U64_PSEUDO [[PHI3]], killed [[S_MOV_B64_]], implicit-def dead $vcc_lo, implicit $exec
7272
; GCN-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 1
7373
; GCN-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = nsw S_ADD_I32 [[PHI2]], killed [[S_MOV_B32_3]], implicit-def dead $scc
7474
; GCN-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 9

‎llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -run-pass machineverifier -o /dev/null %s 2>&1 | FileCheck -check-prefix=GFX12-ERR %s
22

33
# GFX12-ERR: *** Bad machine code: VOP* instruction violates constant bus restriction ***
4-
# GFX12-ERR: $vgpr2, $vgpr3 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx12 $sgpr0, $vgpr0, $sgpr1, $vgpr1, implicit $exec, implicit $mode, implicit $vcc, implicit $vcc_lo
4+
# GFX12-ERR: $vgpr2, $vgpr3 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx12 $sgpr0, $vgpr0, $sgpr1, $vgpr1, implicit $exec, implicit $mode, implicit $vcc_lo, implicit $vcc_lo
55
---
66
name: vopd_cndmask_2sgpr
77
body: |

‎llvm/test/CodeGen/AMDGPU/verify-vopd.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -run-pass machineverifier -o /dev/null %s 2>&1 | FileCheck -check-prefix=GFX11-ERR %s
22

33
# GFX11-ERR: *** Bad machine code: VOP* instruction violates constant bus restriction ***
4-
# GFX11-ERR: $vgpr2, $vgpr3 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx11 $sgpr0, $vgpr0, $sgpr1, $vgpr1, implicit $exec, implicit $mode, implicit $vcc, implicit $vcc_lo
4+
# GFX11-ERR: $vgpr2, $vgpr3 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx11 $sgpr0, $vgpr0, $sgpr1, $vgpr1, implicit $exec, implicit $mode, implicit $vcc_lo, implicit $vcc_lo
55
---
66
name: vopd_cndmask_2sgpr
77
body: |

‎llvm/test/CodeGen/AMDGPU/vopc_dpp.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ body: |
1818
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
1919
; GCN-NEXT: V_CMP_LT_F32_e32_dpp 0, [[COPY1]], 0, [[COPY]], 1, 15, 15, 1, implicit-def $vcc, implicit $mode, implicit $exec
2020
; GCN-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec
21-
; GCN-NEXT: V_CMPX_EQ_I16_t16_nosdst_e64 [[V_MOV_B32_dpp]], [[COPY]], implicit-def $exec, implicit-def $vcc, implicit $mode, implicit $exec
21+
; GCN-NEXT: V_CMPX_EQ_I16_t16_nosdst_e64 [[V_MOV_B32_dpp]], [[COPY]], implicit-def $exec, implicit-def $vcc_lo, implicit $mode, implicit $exec
2222
; GCN-NEXT: [[V_CMP_CLASS_F16_t16_e64_dpp:%[0-9]+]]:sgpr_32 = V_CMP_CLASS_F16_t16_e64_dpp 0, [[COPY1]], [[COPY]], 1, 15, 15, 1, implicit $exec
2323
; GCN-NEXT: [[V_CMP_GE_F16_t16_e64_dpp:%[0-9]+]]:sgpr_32 = V_CMP_GE_F16_t16_e64_dpp 1, [[COPY1]], 0, [[COPY]], 1, 1, 15, 15, 1, implicit $mode, implicit $exec
2424
; GCN-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec
@@ -89,7 +89,7 @@ body: |
8989
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
9090
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
9191
; GCN-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 14, 1, implicit $exec
92-
; GCN-NEXT: [[V_CMP_CLASS_F16_t16_e64_:%[0-9]+]]:sgpr_32 = V_CMP_CLASS_F16_t16_e64 0, [[V_MOV_B32_dpp]], [[COPY]], implicit-def $vcc, implicit $mode, implicit $exec
92+
; GCN-NEXT: [[V_CMP_CLASS_F16_t16_e64_:%[0-9]+]]:sgpr_32 = V_CMP_CLASS_F16_t16_e64 0, [[V_MOV_B32_dpp]], [[COPY]], implicit-def $vcc_lo, implicit $mode, implicit $exec
9393
; GCN-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[V_MOV_B32_e32_]], [[COPY1]], 1, 13, 15, 1, implicit $exec
9494
; GCN-NEXT: [[V_CMP_GE_F32_e64_:%[0-9]+]]:sgpr_32 = V_CMP_GE_F32_e64 1, [[V_MOV_B32_dpp1]], 0, [[COPY]], 1, implicit $mode, implicit $exec
9595
%0:vgpr_32 = COPY $vgpr0

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