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move isRenamedInGFX9 to be static and add helper macro for case prefixes
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2 files changed

+17
-56
lines changed

2 files changed

+17
-56
lines changed

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 17 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -9134,68 +9134,31 @@ bool SIInstrInfo::isAsmOnlyOpcode(int MCOp) const {
91349134
}
91359135
}
91369136

9137-
bool SIInstrInfo::isRenamedInGFX9(int Opcode) const {
9137+
#define GENERATE_RENAMED_GFX9_CASES(OPCODE) \
9138+
case OPCODE##_dpp: \
9139+
case OPCODE##_e32: \
9140+
case OPCODE##_e64: \
9141+
case OPCODE##_e64_dpp: \
9142+
case OPCODE##_sdwa:
9143+
9144+
static bool isRenamedInGFX9(int Opcode) {
91389145
switch (Opcode) {
9139-
case AMDGPU::V_ADDC_U32_dpp:
9140-
case AMDGPU::V_ADDC_U32_e32:
9141-
case AMDGPU::V_ADDC_U32_e64:
9142-
case AMDGPU::V_ADDC_U32_e64_dpp:
9143-
case AMDGPU::V_ADDC_U32_sdwa:
9144-
//
9145-
case AMDGPU::V_ADD_CO_U32_dpp:
9146-
case AMDGPU::V_ADD_CO_U32_e32:
9147-
case AMDGPU::V_ADD_CO_U32_e64:
9148-
case AMDGPU::V_ADD_CO_U32_e64_dpp:
9149-
case AMDGPU::V_ADD_CO_U32_sdwa:
9150-
//
9151-
case AMDGPU::V_ADD_U32_dpp:
9152-
case AMDGPU::V_ADD_U32_e32:
9153-
case AMDGPU::V_ADD_U32_e64:
9154-
case AMDGPU::V_ADD_U32_e64_dpp:
9155-
case AMDGPU::V_ADD_U32_sdwa:
9146+
GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_ADDC_U32)
9147+
GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_ADD_CO_U32)
9148+
GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_ADD_U32)
9149+
GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_SUBBREV_U32)
9150+
GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_SUBB_U32)
9151+
GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_SUBREV_CO_U32)
9152+
GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_SUBREV_U32)
9153+
GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_SUB_CO_U32)
9154+
GENERATE_RENAMED_GFX9_CASES(AMDGPU::V_SUB_U32)
91569155
//
91579156
case AMDGPU::V_DIV_FIXUP_F16_gfx9_e64:
91589157
case AMDGPU::V_FMA_F16_gfx9_e64:
91599158
case AMDGPU::V_INTERP_P2_F16:
91609159
case AMDGPU::V_MAD_F16_e64:
91619160
case AMDGPU::V_MAD_U16_e64:
91629161
case AMDGPU::V_MAD_I16_e64:
9163-
//
9164-
case AMDGPU::V_SUBBREV_U32_dpp:
9165-
case AMDGPU::V_SUBBREV_U32_e32:
9166-
case AMDGPU::V_SUBBREV_U32_e64:
9167-
case AMDGPU::V_SUBBREV_U32_e64_dpp:
9168-
case AMDGPU::V_SUBBREV_U32_sdwa:
9169-
//
9170-
case AMDGPU::V_SUBB_U32_dpp:
9171-
case AMDGPU::V_SUBB_U32_e32:
9172-
case AMDGPU::V_SUBB_U32_e64:
9173-
case AMDGPU::V_SUBB_U32_e64_dpp:
9174-
case AMDGPU::V_SUBB_U32_sdwa:
9175-
//
9176-
case AMDGPU::V_SUBREV_CO_U32_dpp:
9177-
case AMDGPU::V_SUBREV_CO_U32_e32:
9178-
case AMDGPU::V_SUBREV_CO_U32_e64:
9179-
case AMDGPU::V_SUBREV_CO_U32_e64_dpp:
9180-
case AMDGPU::V_SUBREV_CO_U32_sdwa:
9181-
//
9182-
case AMDGPU::V_SUBREV_U32_dpp:
9183-
case AMDGPU::V_SUBREV_U32_e32:
9184-
case AMDGPU::V_SUBREV_U32_e64:
9185-
case AMDGPU::V_SUBREV_U32_e64_dpp:
9186-
case AMDGPU::V_SUBREV_U32_sdwa:
9187-
//
9188-
case AMDGPU::V_SUB_CO_U32_dpp:
9189-
case AMDGPU::V_SUB_CO_U32_e32:
9190-
case AMDGPU::V_SUB_CO_U32_e64:
9191-
case AMDGPU::V_SUB_CO_U32_e64_dpp:
9192-
case AMDGPU::V_SUB_CO_U32_sdwa:
9193-
//
9194-
case AMDGPU::V_SUB_U32_dpp:
9195-
case AMDGPU::V_SUB_U32_e32:
9196-
case AMDGPU::V_SUB_U32_e64:
9197-
case AMDGPU::V_SUB_U32_e64_dpp:
9198-
case AMDGPU::V_SUB_U32_sdwa:
91999162
return true;
92009163
default:
92019164
return false;

llvm/lib/Target/AMDGPU/SIInstrInfo.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1339,8 +1339,6 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
13391339
/// Return true if this opcode should not be used by codegen.
13401340
bool isAsmOnlyOpcode(int MCOp) const;
13411341

1342-
bool isRenamedInGFX9(int Opcode) const;
1343-
13441342
const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
13451343
const TargetRegisterInfo *TRI,
13461344
const MachineFunction &MF)

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