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[LoongArch] Pre-commit tests for vector shift (#132702)
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‎llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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define <16 x i8> @shuffle_to_vslli_h_8(<16 x i8> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vslli_h_8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI0_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
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; CHECK-NEXT: ret
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 0, i32 16, i32 2, i32 16, i32 4, i32 16, i32 6, i32 16, i32 8, i32 16, i32 10, i32 16, i32 12, i32 16, i32 14>
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ret <16 x i8> %shuffle
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}
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define <16 x i8> @shuffle_to_vsrli_h_8(<16 x i8> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vsrli_h_8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI1_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
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; CHECK-NEXT: ret
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 1, i32 16, i32 3, i32 16, i32 5, i32 16, i32 7, i32 16, i32 9, i32 16, i32 11, i32 16, i32 13, i32 16, i32 15, i32 16>
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ret <16 x i8> %shuffle
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}
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define <16 x i8> @shuffle_to_vslli_w_8(<16 x i8> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vslli_w_8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI2_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI2_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
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; CHECK-NEXT: ret
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 0, i32 1, i32 2, i32 16, i32 4, i32 5, i32 6, i32 16, i32 8, i32 9, i32 10, i32 16, i32 12, i32 13, i32 14>
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ret <16 x i8> %shuffle
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}
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define <16 x i8> @shuffle_to_vsrli_w_8(<16 x i8> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vsrli_w_8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI3_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
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; CHECK-NEXT: ret
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 1, i32 2, i32 3, i32 16, i32 5, i32 6, i32 7, i32 16, i32 9, i32 10, i32 11, i32 16, i32 13, i32 14, i32 15, i32 16>
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ret <16 x i8> %shuffle
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}
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define <8 x i16> @shuffle_to_vslli_w_16(<8 x i16> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vslli_w_16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI4_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
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; CHECK-NEXT: vori.b $vr0, $vr1, 0
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; CHECK-NEXT: ret
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%shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 8, i32 0, i32 8, i32 2, i32 8, i32 4, i32 8, i32 6>
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ret <8 x i16> %shuffle
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}
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define <8 x i16> @shuffle_to_vsrli_w_16(<8 x i16> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vsrli_w_16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI5_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI5_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
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; CHECK-NEXT: vori.b $vr0, $vr1, 0
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; CHECK-NEXT: ret
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%shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 1, i32 8, i32 3, i32 8, i32 5, i32 8, i32 7, i32 8>
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ret <8 x i16> %shuffle
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}
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define <16 x i8> @shuffle_to_vslli_w_24(<16 x i8> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vslli_w_24:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI6_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI6_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
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; CHECK-NEXT: ret
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 4, i32 16, i32 16, i32 16, i32 8, i32 16, i32 16, i32 16, i32 12>
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ret <16 x i8> %shuffle
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}
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define <16 x i8> @shuffle_to_vsrli_w_24(<16 x i8> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vsrli_w_24:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI7_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI7_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
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; CHECK-NEXT: ret
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 3, i32 16, i32 16, i32 16, i32 7, i32 16, i32 16, i32 16, i32 11, i32 16, i32 16, i32 16, i32 15, i32 16, i32 16, i32 16>
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ret <16 x i8> %shuffle
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}
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define <16 x i8> @shuffle_to_vslli_d_8(<16 x i8> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vslli_d_8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI8_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI8_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
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; CHECK-NEXT: ret
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 16, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
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ret <16 x i8> %shuffle
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}
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define <16 x i8> @shuffle_to_vsrli_d_8(<16 x i8> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vsrli_d_8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI9_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI9_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
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; CHECK-NEXT: ret
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>
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ret <16 x i8> %shuffle
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}
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define <8 x i16> @shuffle_to_vslli_d_16(<8 x i16> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vslli_d_16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI10_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI10_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
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; CHECK-NEXT: vori.b $vr0, $vr1, 0
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; CHECK-NEXT: ret
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%shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 8, i32 0, i32 1, i32 2, i32 8, i32 4, i32 5, i32 6>
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ret <8 x i16> %shuffle
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}
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define <8 x i16> @shuffle_to_vsrli_d_16(<8 x i16> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vsrli_d_16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI11_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI11_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
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; CHECK-NEXT: vori.b $vr0, $vr1, 0
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; CHECK-NEXT: ret
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%shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 7, i32 8>
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ret <8 x i16> %shuffle
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}
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define <16 x i8> @shuffle_to_vslli_d_24(<16 x i8> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vslli_d_24:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI12_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI12_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
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; CHECK-NEXT: ret
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 16, i32 16, i32 16, i32 8, i32 9, i32 10, i32 11, i32 12>
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ret <16 x i8> %shuffle
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}
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define <16 x i8> @shuffle_to_vsrli_d_24(<16 x i8> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vsrli_d_24:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI13_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI13_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
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; CHECK-NEXT: ret
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 16, i32 16, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16>
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ret <16 x i8> %shuffle
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}
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define <4 x i32> @shuffle_to_vslli_d_32(<4 x i32> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vslli_d_32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI14_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI14_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.w $vr1, $vr2, $vr0
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; CHECK-NEXT: vori.b $vr0, $vr1, 0
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; CHECK-NEXT: ret
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%shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 4, i32 0, i32 4, i32 poison>
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ret <4 x i32> %shuffle
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}
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define <4 x i32> @shuffle_to_vsrli_d_32(<4 x i32> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vsrli_d_32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI15_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI15_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.w $vr1, $vr2, $vr0
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; CHECK-NEXT: vori.b $vr0, $vr1, 0
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; CHECK-NEXT: ret
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%shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
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ret <4 x i32> %shuffle
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}
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define <16 x i8> @shuffle_to_vslli_d_40(<16 x i8> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vslli_d_40:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI16_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI16_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
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; CHECK-NEXT: ret
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 16, i32 16, i32 16, i32 16, i32 16, i32 8, i32 9, i32 10>
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ret <16 x i8> %shuffle
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}
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define <16 x i8> @shuffle_to_vsrli_d_40(<16 x i8> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vsrli_d_40:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI17_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI17_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
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; CHECK-NEXT: ret
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 5, i32 6, i32 7, i32 16, i32 16, i32 16, i32 16, i32 16, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16>
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ret <16 x i8> %shuffle
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}
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define <8 x i16> @shuffle_to_vslli_d_48(<8 x i16> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vslli_d_48:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI18_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI18_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
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; CHECK-NEXT: vori.b $vr0, $vr1, 0
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; CHECK-NEXT: ret
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%shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 8, i32 8, i32 8, i32 0, i32 8, i32 8, i32 8, i32 4>
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ret <8 x i16> %shuffle
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}
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define <8 x i16> @shuffle_to_vsrli_d_48(<8 x i16> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vsrli_d_48:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI19_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI19_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
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; CHECK-NEXT: vori.b $vr0, $vr1, 0
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; CHECK-NEXT: ret
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%shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 3, i32 8, i32 8, i32 8, i32 7, i32 8, i32 8, i32 8>
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ret <8 x i16> %shuffle
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}
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define <16 x i8> @shuffle_to_vslli_d_56(<16 x i8> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vslli_d_56:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI20_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI20_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
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; CHECK-NEXT: ret
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 8>
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ret <16 x i8> %shuffle
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}
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define <16 x i8> @shuffle_to_vsrli_d_56(<16 x i8> %a) nounwind {
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; CHECK-LABEL: shuffle_to_vsrli_d_56:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI21_0)
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; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI21_0)
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; CHECK-NEXT: vrepli.b $vr2, 0
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; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
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; CHECK-NEXT: ret
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 7, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
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ret <16 x i8> %shuffle
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}

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