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[LoongArch] Pre-commit tests for vector shift #132702
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@llvm/pr-subscribers-backend-loongarch Author: None (tangaac) ChangesPatch is 42.10 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/132702.diff 2 Files Affected:
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll
new file mode 100644
index 0000000000000..147a4c549c236
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll
@@ -0,0 +1,274 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+define <16 x i8> @shuffle_to_vslli_h_8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_h_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI0_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 0, i32 16, i32 2, i32 16, i32 4, i32 16, i32 6, i32 16, i32 8, i32 16, i32 10, i32 16, i32 12, i32 16, i32 14>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vsrli_h_8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_h_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI1_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 1, i32 16, i32 3, i32 16, i32 5, i32 16, i32 7, i32 16, i32 9, i32 16, i32 11, i32 16, i32 13, i32 16, i32 15, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vslli_w_8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_w_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI2_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI2_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 0, i32 1, i32 2, i32 16, i32 4, i32 5, i32 6, i32 16, i32 8, i32 9, i32 10, i32 16, i32 12, i32 13, i32 14>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vsrli_w_8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_w_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI3_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 1, i32 2, i32 3, i32 16, i32 5, i32 6, i32 7, i32 16, i32 9, i32 10, i32 11, i32 16, i32 13, i32 14, i32 15, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <8 x i16> @shuffle_to_vslli_w_16(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_w_16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI4_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 8, i32 0, i32 8, i32 2, i32 8, i32 4, i32 8, i32 6>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_to_vsrli_w_16(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_w_16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI5_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI5_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 1, i32 8, i32 3, i32 8, i32 5, i32 8, i32 7, i32 8>
+ ret <8 x i16> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vslli_w_24(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_w_24:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI6_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI6_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 4, i32 16, i32 16, i32 16, i32 8, i32 16, i32 16, i32 16, i32 12>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vsrli_w_24(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_w_24:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI7_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI7_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 3, i32 16, i32 16, i32 16, i32 7, i32 16, i32 16, i32 16, i32 11, i32 16, i32 16, i32 16, i32 15, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vslli_d_8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_d_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI8_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI8_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 16, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vsrli_d_8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_d_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI9_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI9_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <8 x i16> @shuffle_to_vslli_d_16(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_d_16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI10_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI10_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 8, i32 0, i32 1, i32 2, i32 8, i32 4, i32 5, i32 6>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_to_vsrli_d_16(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_d_16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI11_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI11_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 7, i32 8>
+ ret <8 x i16> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vslli_d_24(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_d_24:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI12_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI12_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 16, i32 16, i32 16, i32 8, i32 9, i32 10, i32 11, i32 12>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vsrli_d_24(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_d_24:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI13_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI13_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 16, i32 16, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <4 x i32> @shuffle_to_vslli_d_32(<4 x i32> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_d_32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI14_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI14_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.w $vr1, $vr2, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 4, i32 0, i32 4, i32 poison>
+ ret <4 x i32> %shuffle
+}
+
+define <4 x i32> @shuffle_to_vsrli_d_32(<4 x i32> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_d_32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI15_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI15_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.w $vr1, $vr2, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
+ ret <4 x i32> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vslli_d_40(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_d_40:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI16_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI16_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 16, i32 16, i32 16, i32 16, i32 16, i32 8, i32 9, i32 10>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vsrli_d_40(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_d_40:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI17_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI17_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 5, i32 6, i32 7, i32 16, i32 16, i32 16, i32 16, i32 16, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <8 x i16> @shuffle_to_vslli_d_48(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_d_48:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI18_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI18_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 8, i32 8, i32 8, i32 0, i32 8, i32 8, i32 8, i32 4>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_to_vsrli_d_48(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_d_48:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI19_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI19_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 3, i32 8, i32 8, i32 8, i32 7, i32 8, i32 8, i32 8>
+ ret <8 x i16> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vslli_d_56(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_d_56:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI20_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI20_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 8>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vsrli_d_56(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_d_56:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI21_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI21_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 7, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
\ No newline at end of file
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-byte-shift.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-byte-shift.ll
new file mode 100644
index 0000000000000..a37dbb3267ab4
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-byte-shift.ll
@@ -0,0 +1,645 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_1(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI0_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_2(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI1_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_3(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI2_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI2_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_4(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI3_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_5(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_5:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI4_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_6(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI5_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI5_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_7(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI6_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI6_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI7_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI7_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_9(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_9:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI8_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI8_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_10(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_10:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI9_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI9_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_11(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_11:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI10_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI10_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_12(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_12:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI11_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI11_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_13(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_13:
+; CHECK: # %bb.0:
+; ...
[truncated]
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/51/builds/13182 Here is the relevant piece of the build log for the reference
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