Update RISCVInstrInfo::copyPhysReg with renamable ADDI

Author: BeMg

llvm/lib/CodeGen/TargetInstrInfo.cpp

@@ -823,7 +823,9 @@ void TargetInstrInfo::lowerCopy(MachineInstr *MI,
   }
 
   copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(), DstMO.getReg(),
-              SrcMO.getReg(), SrcMO.isKill());
+              SrcMO.getReg(), SrcMO.isKill(),
+              DstMO.getReg().isPhysical() ? DstMO.isRenamable() : false,
+              SrcMO.getReg().isPhysical() ? SrcMO.isRenamable() : false);
 
   if (MI->getNumOperands() > 2)
     transferImplicitOperands(MI, TRI);

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -446,7 +446,8 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
 
   if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
     BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
-        .addReg(SrcReg, getKillRegState(KillSrc))
+        .addReg(SrcReg,
+                getKillRegState(KillSrc) | getRenamableRegState(RenamableSrc))
         .addImm(0);
     return;
   }

llvm/test/CodeGen/RISCV/renamable-copy.mir

@@ -0,0 +1,31 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -o - %s -mtriple=riscv32 -simplify-mir \
+# RUN:   -run-pass=postrapseudos | FileCheck --check-prefix=RV32 %s
+# RUN: llc -o - %s -mtriple=riscv64 -simplify-mir \
+# RUN:   -run-pass=postrapseudos | FileCheck --check-prefix=RV64 %s
+
+--- |
+  define void @foo() {
+  entry:
+    ret void
+  }
+...
+---
+name:            foo
+body:             |
+  bb.0.entry:
+    liveins: $x11
+    ; RV32-LABEL: name: foo
+    ; RV32: liveins: $x11
+    ; RV32-NEXT: {{  $}}
+    ; RV32-NEXT: $x10 = ADDI renamable $x11, 0
+    ; RV32-NEXT: PseudoRET implicit $x10
+    ;
+    ; RV64-LABEL: name: foo
+    ; RV64: liveins: $x11
+    ; RV64-NEXT: {{  $}}
+    ; RV64-NEXT: $x10 = ADDI renamable $x11, 0
+    ; RV64-NEXT: PseudoRET implicit $x10
+    renamable $x10 = COPY renamable $x11
+    PseudoRET implicit $x10
+...