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davemgreendavemgreen
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Revert "[AArch64][GlobalISel] Add lowering for constant BIT/BIF/BSP"
This reverts commit cb5bad2 as the existing fcopysign code looks like it might be incorrect.
1 parent eaf23b2 commit b4c66f4

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7 files changed

+130
-153
lines changed

7 files changed

+130
-153
lines changed

‎llvm/lib/Target/AArch64/AArch64Combine.td

Lines changed: 1 addition & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -215,14 +215,6 @@ def unmerge_ext_to_unmerge : GICombineRule<
215215
(apply [{ applyUnmergeExtToUnmerge(*${d}, MRI, B, Observer, ${matchinfo}); }])
216216
>;
217217

218-
def regtriple_matchdata : GIDefMatchData<"std::tuple<Register, Register, Register>">;
219-
def or_to_bsp: GICombineRule <
220-
(defs root:$root, regtriple_matchdata:$matchinfo),
221-
(match (wip_match_opcode G_OR):$root,
222-
[{ return matchOrToBSP(*${root}, MRI, ${matchinfo}); }]),
223-
(apply [{ applyOrToBSP(*${root}, MRI, B, ${matchinfo}); }])
224-
>;
225-
226218
// Post-legalization combines which should happen at all optimization levels.
227219
// (E.g. ones that facilitate matching for the selector) For example, matching
228220
// pseudos.
@@ -250,5 +242,5 @@ def AArch64PostLegalizerCombiner
250242
constant_fold_binops, identity_combines,
251243
ptr_add_immed_chain, overlapping_and,
252244
split_store_zero_128, undef_combines,
253-
select_to_minmax, or_to_bsp]> {
245+
select_to_minmax]> {
254246
}

‎llvm/lib/Target/AArch64/AArch64InstrGISel.td

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -215,9 +215,8 @@ def G_PREFETCH : AArch64GenericInstruction {
215215
let hasSideEffects = 1;
216216
}
217217

218-
// Generic instruction for the BSP pseudo. It is expanded into BSP, which
219-
// expands into BSL/BIT/BIF after register allocation.
220-
def G_BSP : AArch64GenericInstruction {
218+
// Generic bitwise insert if true.
219+
def G_BIT : AArch64GenericInstruction {
221220
let OutOperandList = (outs type0:$dst);
222221
let InOperandList = (ins type0:$src1, type0:$src2, type0:$src3);
223222
let hasSideEffects = 0;
@@ -253,7 +252,7 @@ def : GINodeEquiv<G_FCMGTZ, AArch64fcmgtz>;
253252
def : GINodeEquiv<G_FCMLEZ, AArch64fcmlez>;
254253
def : GINodeEquiv<G_FCMLTZ, AArch64fcmltz>;
255254

256-
def : GINodeEquiv<G_BSP, AArch64bsp>;
255+
def : GINodeEquiv<G_BIT, AArch64bit>;
257256

258257
def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
259258

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1790,7 +1790,7 @@ bool AArch64LegalizerInfo::legalizeFCopySign(MachineInstr &MI,
17901790
if (DstSize == 64)
17911791
Mask = MIRBuilder.buildFNeg(VecTy, Mask);
17921792

1793-
auto Sel = MIRBuilder.buildInstr(AArch64::G_BSP, {VecTy}, {Mask, Ins1, Ins2});
1793+
auto Sel = MIRBuilder.buildInstr(AArch64::G_BIT, {VecTy}, {Ins1, Ins2, Mask});
17941794

17951795
// Build an unmerge whose 0th elt is the original G_FCOPYSIGN destination. We
17961796
// want this to eventually become an EXTRACT_SUBREG.

‎llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp

Lines changed: 0 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -338,47 +338,6 @@ void applySplitStoreZero128(MachineInstr &MI, MachineRegisterInfo &MRI,
338338
Store.eraseFromParent();
339339
}
340340

341-
bool matchOrToBSP(MachineInstr &MI, MachineRegisterInfo &MRI,
342-
std::tuple<Register, Register, Register> &MatchInfo) {
343-
const LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
344-
if (!DstTy.isVector())
345-
return false;
346-
347-
Register AO1, AO2, BVO1, BVO2;
348-
if (!mi_match(
349-
MI, MRI,
350-
m_GOr(m_GAnd(m_Reg(AO1), m_Reg(BVO1)), m_GAnd(m_Reg(AO2), m_Reg(BVO2)))))
351-
return false;
352-
353-
auto *BV1 = getOpcodeDef<GBuildVector>(BVO1, MRI);
354-
auto *BV2 = getOpcodeDef<GBuildVector>(BVO2, MRI);
355-
if (!BV1 || !BV2)
356-
return false;
357-
358-
for (int I = 0, E = DstTy.getNumElements(); I < E; I++) {
359-
auto ValAndVReg1 =
360-
getIConstantVRegValWithLookThrough(BV1->getSourceReg(I), MRI);
361-
auto ValAndVReg2 =
362-
getIConstantVRegValWithLookThrough(BV2->getSourceReg(I), MRI);
363-
if (!ValAndVReg1 || !ValAndVReg2 ||
364-
ValAndVReg1->Value != ~ValAndVReg2->Value)
365-
return false;
366-
}
367-
368-
MatchInfo = {AO1, AO2, BVO2};
369-
return true;
370-
}
371-
372-
void applyOrToBSP(MachineInstr &MI, MachineRegisterInfo &MRI,
373-
MachineIRBuilder &B,
374-
std::tuple<Register, Register, Register> &MatchInfo) {
375-
B.setInstrAndDebugLoc(MI);
376-
B.buildInstr(
377-
AArch64::G_BSP, {MI.getOperand(0).getReg()},
378-
{std::get<2>(MatchInfo), std::get<0>(MatchInfo), std::get<1>(MatchInfo)});
379-
MI.eraseFromParent();
380-
}
381-
382341
class AArch64PostLegalizerCombinerImpl : public Combiner {
383342
protected:
384343
// TODO: Make CombinerHelper methods const.

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir

Lines changed: 24 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -10,19 +10,18 @@ body: |
1010
liveins: $s0, $s1
1111
; CHECK-LABEL: name: legalize_s32
1212
; CHECK: liveins: $s0, $s1
13-
; CHECK-NEXT: {{ $}}
14-
; CHECK-NEXT: %val:_(s32) = COPY $s0
15-
; CHECK-NEXT: %sign:_(s32) = COPY $s1
16-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
17-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
18-
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %val(s32), [[C]](s32)
19-
; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %sign(s32), [[C]](s32)
20-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
21-
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
22-
; CHECK-NEXT: [[BSP:%[0-9]+]]:_(<4 x s32>) = G_BSP [[BUILD_VECTOR]], [[IVEC]], [[IVEC1]]
23-
; CHECK-NEXT: %fcopysign:_(s32), %10:_(s32), %11:_(s32), %12:_(s32) = G_UNMERGE_VALUES [[BSP]](<4 x s32>)
24-
; CHECK-NEXT: $s0 = COPY %fcopysign(s32)
25-
; CHECK-NEXT: RET_ReallyLR implicit $s0
13+
; CHECK: %val:_(s32) = COPY $s0
14+
; CHECK: %sign:_(s32) = COPY $s1
15+
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
16+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
17+
; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %val(s32), [[C]](s32)
18+
; CHECK: [[IVEC1:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %sign(s32), [[C]](s32)
19+
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
20+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
21+
; CHECK: [[BIT:%[0-9]+]]:_(<4 x s32>) = G_BIT [[IVEC]], [[IVEC1]], [[BUILD_VECTOR]]
22+
; CHECK: %fcopysign:_(s32), %10:_(s32), %11:_(s32), %12:_(s32) = G_UNMERGE_VALUES [[BIT]](<4 x s32>)
23+
; CHECK: $s0 = COPY %fcopysign(s32)
24+
; CHECK: RET_ReallyLR implicit $s0
2625
%val:_(s32) = COPY $s0
2726
%sign:_(s32) = COPY $s1
2827
%fcopysign:_(s32) = G_FCOPYSIGN %val, %sign(s32)
@@ -38,19 +37,18 @@ body: |
3837
liveins: $d0, $d1
3938
; CHECK-LABEL: name: legalize_s64
4039
; CHECK: liveins: $d0, $d1
41-
; CHECK-NEXT: {{ $}}
42-
; CHECK-NEXT: %val:_(s64) = COPY $d0
43-
; CHECK-NEXT: %sign:_(s64) = COPY $d1
44-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
45-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
46-
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], %val(s64), [[C]](s64)
47-
; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], %sign(s64), [[C]](s64)
48-
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
49-
; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(<2 x s64>) = G_FNEG [[BUILD_VECTOR]]
50-
; CHECK-NEXT: [[BSP:%[0-9]+]]:_(<2 x s64>) = G_BSP [[FNEG]], [[IVEC]], [[IVEC1]]
51-
; CHECK-NEXT: %fcopysign:_(s64), %10:_(s64) = G_UNMERGE_VALUES [[BSP]](<2 x s64>)
52-
; CHECK-NEXT: $d0 = COPY %fcopysign(s64)
53-
; CHECK-NEXT: RET_ReallyLR implicit $d0
40+
; CHECK: %val:_(s64) = COPY $d0
41+
; CHECK: %sign:_(s64) = COPY $d1
42+
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
43+
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
44+
; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], %val(s64), [[C]](s64)
45+
; CHECK: [[IVEC1:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], %sign(s64), [[C]](s64)
46+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
47+
; CHECK: [[FNEG:%[0-9]+]]:_(<2 x s64>) = G_FNEG [[BUILD_VECTOR]]
48+
; CHECK: [[BIT:%[0-9]+]]:_(<2 x s64>) = G_BIT [[IVEC]], [[IVEC1]], [[FNEG]]
49+
; CHECK: %fcopysign:_(s64), %10:_(s64) = G_UNMERGE_VALUES [[BIT]](<2 x s64>)
50+
; CHECK: $d0 = COPY %fcopysign(s64)
51+
; CHECK: RET_ReallyLR implicit $d0
5452
%val:_(s64) = COPY $d0
5553
%sign:_(s64) = COPY $d1
5654
%fcopysign:_(s64) = G_FCOPYSIGN %val, %sign(s64)

‎llvm/test/CodeGen/AArch64/GlobalISel/select-bit.mir

Lines changed: 42 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -13,17 +13,16 @@ body: |
1313
1414
; CHECK-LABEL: name: BITv8i8_v2s32
1515
; CHECK: liveins: $d0, $d1, $d2
16-
; CHECK-NEXT: {{ $}}
17-
; CHECK-NEXT: %lhs:fpr64 = COPY $d0
18-
; CHECK-NEXT: %mhs:fpr64 = COPY $d1
19-
; CHECK-NEXT: %rhs:fpr64 = COPY $d2
20-
; CHECK-NEXT: %bit:fpr64 = BSPv8i8 %lhs, %mhs, %rhs
21-
; CHECK-NEXT: $d0 = COPY %bit
22-
; CHECK-NEXT: RET_ReallyLR implicit $d0
16+
; CHECK: %lhs:fpr64 = COPY $d0
17+
; CHECK: %mhs:fpr64 = COPY $d1
18+
; CHECK: %rhs:fpr64 = COPY $d2
19+
; CHECK: %bit:fpr64 = BITv8i8 %lhs, %mhs, %rhs
20+
; CHECK: $d0 = COPY %bit
21+
; CHECK: RET_ReallyLR implicit $d0
2322
%lhs:fpr(<2 x s32>) = COPY $d0
2423
%mhs:fpr(<2 x s32>) = COPY $d1
2524
%rhs:fpr(<2 x s32>) = COPY $d2
26-
%bit:fpr(<2 x s32>) = G_BSP %lhs, %mhs, %rhs
25+
%bit:fpr(<2 x s32>) = G_BIT %lhs, %mhs, %rhs
2726
$d0 = COPY %bit(<2 x s32>)
2827
RET_ReallyLR implicit $d0
2928
@@ -38,17 +37,16 @@ body: |
3837
liveins: $d0, $d1, $d2
3938
; CHECK-LABEL: name: BITv8i8_v4s16
4039
; CHECK: liveins: $d0, $d1, $d2
41-
; CHECK-NEXT: {{ $}}
42-
; CHECK-NEXT: %lhs:fpr64 = COPY $d0
43-
; CHECK-NEXT: %mhs:fpr64 = COPY $d1
44-
; CHECK-NEXT: %rhs:fpr64 = COPY $d2
45-
; CHECK-NEXT: %bit:fpr64 = BSPv8i8 %lhs, %mhs, %rhs
46-
; CHECK-NEXT: $d0 = COPY %bit
47-
; CHECK-NEXT: RET_ReallyLR implicit $d0
40+
; CHECK: %lhs:fpr64 = COPY $d0
41+
; CHECK: %mhs:fpr64 = COPY $d1
42+
; CHECK: %rhs:fpr64 = COPY $d2
43+
; CHECK: %bit:fpr64 = BITv8i8 %lhs, %mhs, %rhs
44+
; CHECK: $d0 = COPY %bit
45+
; CHECK: RET_ReallyLR implicit $d0
4846
%lhs:fpr(<4 x s16>) = COPY $d0
4947
%mhs:fpr(<4 x s16>) = COPY $d1
5048
%rhs:fpr(<4 x s16>) = COPY $d2
51-
%bit:fpr(<4 x s16>) = G_BSP %lhs, %mhs, %rhs
49+
%bit:fpr(<4 x s16>) = G_BIT %lhs, %mhs, %rhs
5250
$d0 = COPY %bit(<4 x s16>)
5351
RET_ReallyLR implicit $d0
5452
@@ -64,17 +62,16 @@ body: |
6462
6563
; CHECK-LABEL: name: BITv16i8_v2s64
6664
; CHECK: liveins: $q0, $q1, $q2
67-
; CHECK-NEXT: {{ $}}
68-
; CHECK-NEXT: %lhs:fpr128 = COPY $q0
69-
; CHECK-NEXT: %mhs:fpr128 = COPY $q1
70-
; CHECK-NEXT: %rhs:fpr128 = COPY $q2
71-
; CHECK-NEXT: %bit:fpr128 = BSPv16i8 %lhs, %mhs, %rhs
72-
; CHECK-NEXT: $q0 = COPY %bit
73-
; CHECK-NEXT: RET_ReallyLR implicit $q0
65+
; CHECK: %lhs:fpr128 = COPY $q0
66+
; CHECK: %mhs:fpr128 = COPY $q1
67+
; CHECK: %rhs:fpr128 = COPY $q2
68+
; CHECK: %bit:fpr128 = BITv16i8 %lhs, %mhs, %rhs
69+
; CHECK: $q0 = COPY %bit
70+
; CHECK: RET_ReallyLR implicit $q0
7471
%lhs:fpr(<2 x s64>) = COPY $q0
7572
%mhs:fpr(<2 x s64>) = COPY $q1
7673
%rhs:fpr(<2 x s64>) = COPY $q2
77-
%bit:fpr(<2 x s64>) = G_BSP %lhs, %mhs, %rhs
74+
%bit:fpr(<2 x s64>) = G_BIT %lhs, %mhs, %rhs
7875
$q0 = COPY %bit(<2 x s64>)
7976
RET_ReallyLR implicit $q0
8077
@@ -90,17 +87,16 @@ body: |
9087
9188
; CHECK-LABEL: name: BITv16i8_v4s32
9289
; CHECK: liveins: $q0, $q1, $q2
93-
; CHECK-NEXT: {{ $}}
94-
; CHECK-NEXT: %lhs:fpr128 = COPY $q0
95-
; CHECK-NEXT: %mhs:fpr128 = COPY $q1
96-
; CHECK-NEXT: %rhs:fpr128 = COPY $q2
97-
; CHECK-NEXT: %bit:fpr128 = BSPv16i8 %lhs, %mhs, %rhs
98-
; CHECK-NEXT: $q0 = COPY %bit
99-
; CHECK-NEXT: RET_ReallyLR implicit $q0
90+
; CHECK: %lhs:fpr128 = COPY $q0
91+
; CHECK: %mhs:fpr128 = COPY $q1
92+
; CHECK: %rhs:fpr128 = COPY $q2
93+
; CHECK: %bit:fpr128 = BITv16i8 %lhs, %mhs, %rhs
94+
; CHECK: $q0 = COPY %bit
95+
; CHECK: RET_ReallyLR implicit $q0
10096
%lhs:fpr(<4 x s32>) = COPY $q0
10197
%mhs:fpr(<4 x s32>) = COPY $q1
10298
%rhs:fpr(<4 x s32>) = COPY $q2
103-
%bit:fpr(<4 x s32>) = G_BSP %lhs, %mhs, %rhs
99+
%bit:fpr(<4 x s32>) = G_BIT %lhs, %mhs, %rhs
104100
$q0 = COPY %bit(<4 x s32>)
105101
RET_ReallyLR implicit $q0
106102
@@ -116,17 +112,16 @@ body: |
116112
117113
; CHECK-LABEL: name: BITv16i8_v8s16
118114
; CHECK: liveins: $q0, $q1, $q2
119-
; CHECK-NEXT: {{ $}}
120-
; CHECK-NEXT: %lhs:fpr128 = COPY $q0
121-
; CHECK-NEXT: %mhs:fpr128 = COPY $q1
122-
; CHECK-NEXT: %rhs:fpr128 = COPY $q2
123-
; CHECK-NEXT: %bit:fpr128 = BSPv16i8 %lhs, %mhs, %rhs
124-
; CHECK-NEXT: $q0 = COPY %bit
125-
; CHECK-NEXT: RET_ReallyLR implicit $q0
115+
; CHECK: %lhs:fpr128 = COPY $q0
116+
; CHECK: %mhs:fpr128 = COPY $q1
117+
; CHECK: %rhs:fpr128 = COPY $q2
118+
; CHECK: %bit:fpr128 = BITv16i8 %lhs, %mhs, %rhs
119+
; CHECK: $q0 = COPY %bit
120+
; CHECK: RET_ReallyLR implicit $q0
126121
%lhs:fpr(<8 x s16>) = COPY $q0
127122
%mhs:fpr(<8 x s16>) = COPY $q1
128123
%rhs:fpr(<8 x s16>) = COPY $q2
129-
%bit:fpr(<8 x s16>) = G_BSP %lhs, %mhs, %rhs
124+
%bit:fpr(<8 x s16>) = G_BIT %lhs, %mhs, %rhs
130125
$q0 = COPY %bit(<8 x s16>)
131126
RET_ReallyLR implicit $q0
132127
@@ -142,16 +137,15 @@ body: |
142137
143138
; CHECK-LABEL: name: BITv16i8_v16s8
144139
; CHECK: liveins: $q0, $q1, $q2
145-
; CHECK-NEXT: {{ $}}
146-
; CHECK-NEXT: %lhs:fpr128 = COPY $q0
147-
; CHECK-NEXT: %mhs:fpr128 = COPY $q1
148-
; CHECK-NEXT: %rhs:fpr128 = COPY $q2
149-
; CHECK-NEXT: %bit:fpr128 = BSPv16i8 %lhs, %mhs, %rhs
150-
; CHECK-NEXT: $q0 = COPY %bit
151-
; CHECK-NEXT: RET_ReallyLR implicit $q0
140+
; CHECK: %lhs:fpr128 = COPY $q0
141+
; CHECK: %mhs:fpr128 = COPY $q1
142+
; CHECK: %rhs:fpr128 = COPY $q2
143+
; CHECK: %bit:fpr128 = BITv16i8 %lhs, %mhs, %rhs
144+
; CHECK: $q0 = COPY %bit
145+
; CHECK: RET_ReallyLR implicit $q0
152146
%lhs:fpr(<16 x s8>) = COPY $q0
153147
%mhs:fpr(<16 x s8>) = COPY $q1
154148
%rhs:fpr(<16 x s8>) = COPY $q2
155-
%bit:fpr(<16 x s8>) = G_BSP %lhs, %mhs, %rhs
149+
%bit:fpr(<16 x s8>) = G_BIT %lhs, %mhs, %rhs
156150
$q0 = COPY %bit(<16 x s8>)
157151
RET_ReallyLR implicit $q0

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