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kstoimenovkstoimenov
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Revert HWASAN failure (#74163)
This is the failure: https://lab.llvm.org/buildbot/#/builders/236/builds/7728/steps/10/logs/stdio This started with eef8e1d, but because there were a couple of patches that came after that I had to revert all 3 of them because of merge conflicts.
1 parent 28eead0 commit b6d0ee0

19 files changed

+7
-336
lines changed

‎clang/test/Driver/aarch64-v95a.c

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,3 @@
1313
// RUN: %clang -target aarch64_be -mbig-endian -march=armv9.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s
1414
// GENERICV95A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.5a"
1515

16-
// ===== Features supported on aarch64 =====
17-
18-
// RUN: %clang -target aarch64 -march=armv9.5a+cpa -### -c %s 2>&1 | FileCheck -check-prefix=V95A-CPA %s
19-
// RUN: %clang -target aarch64 -march=armv9.5-a+cpa -### -c %s 2>&1 | FileCheck -check-prefix=V95A-CPA %s
20-
// V95A-CPA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.5a" "-target-feature" "+cpa"

‎llvm/include/llvm/TargetParser/AArch64TargetParser.h

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -173,7 +173,6 @@ enum ArchExtKind : unsigned {
173173
AEK_SMEF8F16 = 69, // FEAT_SME_F8F16
174174
AEK_SMEF8F32 = 70, // FEAT_SME_F8F32
175175
AEK_SMEFA64 = 71, // FEAT_SME_FA64
176-
AEK_CPA = 72, // FEAT_CPA
177176
AEK_NUM_EXTENSIONS
178177
};
179178
using ExtensionBitset = Bitset<AEK_NUM_EXTENSIONS>;
@@ -296,7 +295,6 @@ inline constexpr ExtensionInfo Extensions[] = {
296295
{"sme-f8f16", AArch64::AEK_SMEF8F16, "+sme-f8f16", "-sme-f8f16", FEAT_INIT, "+sme2,+fp8", 0},
297296
{"sme-f8f32", AArch64::AEK_SMEF8F32, "+sme-f8f32", "-sme-f8f32", FEAT_INIT, "+sme2,+fp8", 0},
298297
{"sme-fa64", AArch64::AEK_SMEFA64, "+sme-fa64", "-sme-fa64", FEAT_INIT, "", 0},
299-
{"cpa", AArch64::AEK_CPA, "+cpa", "-cpa", FEAT_INIT, "", 0},
300298
// Special cases
301299
{"none", AArch64::AEK_NONE, {}, {}, FEAT_INIT, "", ExtensionInfo::MaxFMVPriority},
302300
};
@@ -380,8 +378,7 @@ inline constexpr ArchInfo ARMV9_3A = { VersionTuple{9, 3}, AProfile, "armv9.3-a
380378
AArch64::ExtensionBitset({AArch64::AEK_MOPS, AArch64::AEK_HBC}))};
381379
inline constexpr ArchInfo ARMV9_4A = { VersionTuple{9, 4}, AProfile, "armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts |
382380
AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC, AArch64::AEK_RASv2}))};
383-
inline constexpr ArchInfo ARMV9_5A = { VersionTuple{9, 5}, AProfile, "armv9.5-a", "+v9.5a", (ARMV9_4A.DefaultExts |
384-
AArch64::ExtensionBitset({AArch64::AEK_CPA}))};
381+
inline constexpr ArchInfo ARMV9_5A = { VersionTuple{9, 5}, AProfile, "armv9.5-a", "+v9.5a", (ARMV9_4A.DefaultExts)};
385382
// For v8-R, we do not enable crypto and align with GCC that enables a more minimal set of optional architecture extensions.
386383
inline constexpr ArchInfo ARMV8R = { VersionTuple{8, 0}, RProfile, "armv8-r", "+v8r", (ARMV8_5A.DefaultExts |
387384
AArch64::ExtensionBitset({AArch64::AEK_SSBS,

‎llvm/lib/Target/AArch64/AArch64.td

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -622,9 +622,6 @@ def FeatureLdpAlignedOnly : SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
622622
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only", "HasStpAlignedOnly",
623623
"true", "In order to emit stp, first check if the store will be aligned to 2 * element_size">;
624624

625-
def FeatureCPA : SubtargetFeature<"cpa", "HasCPA", "true",
626-
"Enable ARMv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">;
627-
628625
//===----------------------------------------------------------------------===//
629626
// Architectures.
630627
//
@@ -695,7 +692,7 @@ def HasV9_4aOps : SubtargetFeature<
695692

696693
def HasV9_5aOps : SubtargetFeature<
697694
"v9.5a", "HasV9_5aOps", "true", "Support ARM v9.5a instructions",
698-
[HasV9_4aOps, FeatureCPA]>;
695+
[HasV9_4aOps]>;
699696

700697
def HasV8_0rOps : SubtargetFeature<
701698
"v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions",

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td

Lines changed: 0 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -12446,58 +12446,6 @@ class SystemPXtI<bit L, string asm> :
1244612446
BaseSYSPEncoding<L, asm, "\t$op1, $Cn, $Cm, $op2, $Rt", (outs),
1244712447
(ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XSeqPairClassOperand:$Rt)>;
1244812448

12449-
//----------------------------------------------------------------------------
12450-
// 2023 Armv9.5 Extensions
12451-
//----------------------------------------------------------------------------
12452-
12453-
//---
12454-
// Checked Pointer Arithmetic (FEAT_CPA)
12455-
//---
12456-
12457-
def LSLImm3ShiftOperand : AsmOperandClass {
12458-
let SuperClasses = [ExtendOperandLSL64];
12459-
let Name = "LSLImm3Shift";
12460-
let RenderMethod = "addLSLImm3ShifterOperands";
12461-
let DiagnosticType = "AddSubLSLImm3ShiftLarge";
12462-
}
12463-
12464-
def lsl_imm3_shift_operand : Operand<i32> {
12465-
let PrintMethod = "printShifter";
12466-
let ParserMatchClass = LSLImm3ShiftOperand;
12467-
}
12468-
12469-
// Base CPA scalar add/subtract with lsl #imm3 shift
12470-
class BaseAddSubCPA<bit isSub, string asm> : I<(outs GPR64sp:$Rd),
12471-
(ins GPR64sp:$Rn, GPR64:$Rm, lsl_imm3_shift_operand:$shift_imm),
12472-
asm, "\t$Rd, $Rn, $Rm$shift_imm", "", []>, Sched<[]> {
12473-
bits<5> Rd;
12474-
bits<5> Rn;
12475-
bits<5> Rm;
12476-
bits<3> shift_imm;
12477-
let Inst{31} = 0b1;
12478-
let Inst{30} = isSub;
12479-
let Inst{29-21} = 0b011010000;
12480-
let Inst{20-16} = Rm;
12481-
let Inst{15-13} = 0b001;
12482-
let Inst{12-10} = shift_imm;
12483-
let Inst{9-5} = Rn;
12484-
let Inst{4-0} = Rd;
12485-
}
12486-
12487-
// Alias for CPA scalar add/subtract with no shift
12488-
class AddSubCPAAlias<string asm, Instruction inst>
12489-
: InstAlias<asm#"\t$Rd, $Rn, $Rm",
12490-
(inst GPR64sp:$Rd, GPR64sp:$Rn, GPR64:$Rm, 0)>;
12491-
12492-
multiclass AddSubCPA<bit isSub, string asm> {
12493-
def _shift : BaseAddSubCPA<isSub, asm>;
12494-
def _noshift : AddSubCPAAlias<asm, !cast<Instruction>(NAME#"_shift")>;
12495-
}
12496-
12497-
class MulAccumCPA<bit isSub, string asm>
12498-
: BaseMulAccum<isSub, 0b011, GPR64, GPR64, asm, []>, Sched<[]> {
12499-
let Inst{31} = 0b1;
12500-
}
1250112449

1250212450
//----------------------------------------------------------------------------
1250312451
// Allow the size specifier tokens to be upper case, not just lower.

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 0 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -289,8 +289,6 @@ def HasCHK : Predicate<"Subtarget->hasCHK()">,
289289
AssemblerPredicateWithAll<(all_of FeatureCHK), "chk">;
290290
def HasGCS : Predicate<"Subtarget->hasGCS()">,
291291
AssemblerPredicateWithAll<(all_of FeatureGCS), "gcs">;
292-
def HasCPA : Predicate<"Subtarget->hasCPA()">,
293-
AssemblerPredicateWithAll<(all_of FeatureCPA), "cpa">;
294292
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
295293
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
296294
def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
@@ -9390,10 +9388,6 @@ let Predicates = [HasD128] in {
93909388
}
93919389
}
93929390

9393-
//===----------------------------===//
9394-
// 2023 Architecture Extensions:
9395-
//===----------------------------===//
9396-
93979391
let Predicates = [HasFP8] in {
93989392
defm F1CVTL : SIMDMixedTwoVectorFP8<0b00, "f1cvtl">;
93999393
defm F2CVTL : SIMDMixedTwoVectorFP8<0b01, "f2cvtl">;
@@ -9435,19 +9429,6 @@ let Predicates = [HasFP8DOT4] in {
94359429
defm FDOT : SIMDThreeSameVectorDOT4<"fdot">;
94369430
} // End let Predicates = [HasFP8DOT4]
94379431

9438-
//===----------------------------------------------------------------------===//
9439-
// Checked Pointer Arithmetic (FEAT_CPA)
9440-
//===----------------------------------------------------------------------===//
9441-
let Predicates = [HasCPA] in {
9442-
// Scalar add/subtract
9443-
defm ADDPT : AddSubCPA<0, "addpt">;
9444-
defm SUBPT : AddSubCPA<1, "subpt">;
9445-
9446-
// Scalar multiply-add/subtract
9447-
def MADDPT : MulAccumCPA<0, "maddpt">;
9448-
def MSUBPT : MulAccumCPA<1, "msubpt">;
9449-
}
9450-
94519432
include "AArch64InstrAtomics.td"
94529433
include "AArch64SVEInstrInfo.td"
94539434
include "AArch64SMEInstrInfo.td"

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 0 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -4163,24 +4163,3 @@ let Predicates = [HasSVE2orSME2, HasLUT] in {
41634163
// LUTI4 (two contiguous registers)
41644164
defm LUTI4_Z2ZZI : sve2_luti4_vector_vg2_index<"luti4">;
41654165
} // End HasSVE2orSME2, HasLUT
4166-
4167-
//===----------------------------------------------------------------------===//
4168-
// Checked Pointer Arithmetic (FEAT_CPA)
4169-
//===----------------------------------------------------------------------===//
4170-
let Predicates = [HasSVE, HasCPA] in {
4171-
// Add/subtract (vectors, unpredicated)
4172-
def ADD_ZZZ_CPA : sve_int_bin_cons_arit_0<0b11, 0b010, "addpt", ZPR64>;
4173-
def SUB_ZZZ_CPA : sve_int_bin_cons_arit_0<0b11, 0b011, "subpt", ZPR64>;
4174-
4175-
// Add/subtract (vectors, predicated)
4176-
let DestructiveInstType = DestructiveBinaryComm in {
4177-
def ADD_ZPmZ_CPA : sve_int_bin_pred_arit_log<0b11, 0b00, 0b100, "addpt", ZPR64>;
4178-
def SUB_ZPmZ_CPA : sve_int_bin_pred_arit_log<0b11, 0b00, 0b101, "subpt", ZPR64>;
4179-
}
4180-
4181-
// Multiply-add vectors, writing multiplicand
4182-
def MAD_CPA : sve_int_mad_cpa<"madpt">;
4183-
4184-
// Multiply-add vectors, writing addend
4185-
def MLA_CPA : sve_int_mla_cpa<"mlapt">;
4186-
}

‎llvm/lib/Target/AArch64/AArch64SchedA64FX.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ def A64FXModel : SchedMachineModel {
2424
[HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, HasSVE2BitPerm, HasPAuth,
2525
HasSVE2orSME, HasMTE, HasMatMulInt8, HasBF16, HasSME2, HasSME2p1, HasSVE2p1,
2626
HasSVE2p1_or_HasSME2p1, HasSMEF16F16, HasSSVE_FP8FMA, HasSMEF8F16, HasSMEF8F32,
27-
HasSMEFA64, HasCPA];
27+
HasSMEFA64];
2828

2929
let FullInstRWOverlapCheck = 0;
3030
}

‎llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ def NeoverseN2Model : SchedMachineModel {
1919
let CompleteModel = 1;
2020

2121
list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
22-
[HasSVE2p1, HasCPA]);
22+
[HasSVE2p1]);
2323
}
2424

2525
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ def NeoverseV1Model : SchedMachineModel {
2828

2929
list<Predicate> UnsupportedFeatures = !listconcat(SVE2Unsupported.F,
3030
SMEUnsupported.F,
31-
[HasMTE, HasCPA]);
31+
[HasMTE]);
3232
}
3333

3434
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ def NeoverseV2Model : SchedMachineModel {
2222
let CompleteModel = 1;
2323

2424
list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
25-
[HasSVE2p1, HasCPA]);
25+
[HasSVE2p1]);
2626
}
2727

2828
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Lines changed: 0 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1541,13 +1541,6 @@ class AArch64Operand : public MCParsedAsmOperand {
15411541
getShiftExtendAmount() <= 4;
15421542
}
15431543

1544-
bool isLSLImm3Shift() const {
1545-
if (!isShiftExtend())
1546-
return false;
1547-
AArch64_AM::ShiftExtendType ET = getShiftExtendType();
1548-
return ET == AArch64_AM::LSL && getShiftExtendAmount() <= 7;
1549-
}
1550-
15511544
template<int Width> bool isMemXExtend() const {
15521545
if (!isExtend())
15531546
return false;
@@ -2098,12 +2091,6 @@ class AArch64Operand : public MCParsedAsmOperand {
20982091
Inst.addOperand(MCOperand::createImm(Imm));
20992092
}
21002093

2101-
void addLSLImm3ShifterOperands(MCInst &Inst, unsigned N) const {
2102-
assert(N == 1 && "Invalid number of operands!");
2103-
unsigned Imm = getShiftExtendAmount();
2104-
Inst.addOperand(MCOperand::createImm(Imm));
2105-
}
2106-
21072094
void addSyspXzrPairOperand(MCInst &Inst, unsigned N) const {
21082095
assert(N == 1 && "Invalid number of operands!");
21092096

@@ -3677,7 +3664,6 @@ static const struct Extension {
36773664
{"sme-f8f16", {AArch64::FeatureSMEF8F16}},
36783665
{"sme-f8f32", {AArch64::FeatureSMEF8F32}},
36793666
{"sme-fa64", {AArch64::FeatureSMEFA64}},
3680-
{"cpa", {AArch64::FeatureCPA}},
36813667
};
36823668

36833669
static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
@@ -6078,9 +6064,6 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
60786064
"Invalid vector list, expected list with each SVE vector in the list "
60796065
"4 registers apart, and the first register in the range [z0, z3] or "
60806066
"[z16, z19] and with correct element type");
6081-
case Match_AddSubLSLImm3ShiftLarge:
6082-
return Error(Loc,
6083-
"expected 'lsl' with optional integer in range [0, 7]");
60846067
default:
60856068
llvm_unreachable("unexpected error code!");
60866069
}
@@ -6465,7 +6448,6 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
64656448
case Match_InvalidMemoryIndexed8:
64666449
case Match_InvalidMemoryIndexed16:
64676450
case Match_InvalidCondCode:
6468-
case Match_AddSubLSLImm3ShiftLarge:
64696451
case Match_AddSubRegExtendSmall:
64706452
case Match_AddSubRegExtendLarge:
64716453
case Match_AddSubSecondSource:

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 0 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -10424,34 +10424,3 @@ multiclass sve2_luti4_vector_vg2_index<string mnemonic> {
1042410424
let Inst{23-22} = idx;
1042510425
}
1042610426
}
10427-
10428-
//===----------------------------------------------------------------------===//
10429-
// Checked Pointer Arithmetic (FEAT_CPA)
10430-
//===----------------------------------------------------------------------===//
10431-
class sve_int_mad_cpa<string asm>
10432-
: I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, ZPR64:$Zm, ZPR64:$Za),
10433-
asm, "\t$Zdn, $Zm, $Za", "", []>, Sched<[]> {
10434-
bits<5> Zdn;
10435-
bits<5> Zm;
10436-
bits<5> Za;
10437-
let Inst{31-24} = 0b01000100;
10438-
let Inst{23-22} = 0b11; // sz
10439-
let Inst{21} = 0b0;
10440-
let Inst{20-16} = Zm;
10441-
let Inst{15} = 0b1;
10442-
let Inst{14-10} = 0b10110; // opc
10443-
let Inst{9-5} = Za;
10444-
let Inst{4-0} = Zdn;
10445-
10446-
let Constraints = "$Zdn = $_Zdn";
10447-
let DestructiveInstType = DestructiveOther;
10448-
let ElementSize = ZPR64.ElementSize;
10449-
let hasSideEffects = 0;
10450-
}
10451-
10452-
class sve_int_mla_cpa<string asm>
10453-
: sve2_int_mla<0b11, 0b10100, asm, ZPR64, ZPR64> {
10454-
let Inst{15} = 0b1;
10455-
10456-
let ElementSize = ZPR64.ElementSize;
10457-
}

‎llvm/test/MC/AArch64/SVE/armv9.5a-cpa.s

Lines changed: 0 additions & 69 deletions
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