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changpengchangpeng
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AMDGPU: Implement i1 to bfloat conversion (#130831)
We are using the same approach as the conversion of other integer type to bfloat: i1 --> f32 and f32 --> bf16. Refer to LowerUINT_TO_FP and LowerSINT_TO_FP in AMDGPUTargetLowering.cpp for details. Fixes: SWDEV-511605
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‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

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@@ -582,6 +582,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
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setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, MVT::i16, Custom);
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setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, MVT::i16, Custom);
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setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, MVT::i1, Custom);
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setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, MVT::i32, Custom);
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‎llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll

Lines changed: 292 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx942 | FileCheck %s -check-prefix=GFX942
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define bfloat @v_uitofp_i1_to_bf16(i1 %num) {
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; GFX942-LABEL: v_uitofp_i1_to_bf16:
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; GFX942: ; %bb.0:
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; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8+
; GFX942-NEXT: v_and_b32_e32 v0, 1, v0
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; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; GFX942-NEXT: s_movk_i32 s0, 0x7fff
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; GFX942-NEXT: s_nop 0
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; GFX942-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
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; GFX942-NEXT: v_bfe_u32 v1, v0, 16, 1
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; GFX942-NEXT: v_add3_u32 v1, v1, v0, s0
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; GFX942-NEXT: v_or_b32_e32 v2, 0x400000, v0
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; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
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; GFX942-NEXT: s_nop 1
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; GFX942-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
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; GFX942-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; GFX942-NEXT: s_setpc_b64 s[30:31]
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%op = uitofp i1 %num to bfloat
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ret bfloat %op
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}
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define <2 x bfloat> @v_uitofp_v2i1_to_v2bf16(<2 x i1> %num) {
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; GFX942-LABEL: v_uitofp_v2i1_to_v2bf16:
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; GFX942: ; %bb.0:
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; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX942-NEXT: v_and_b32_e32 v0, 1, v0
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; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; GFX942-NEXT: s_movk_i32 s0, 0x7fff
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; GFX942-NEXT: v_and_b32_e32 v1, 1, v1
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; GFX942-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
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; GFX942-NEXT: v_bfe_u32 v2, v0, 16, 1
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; GFX942-NEXT: v_add3_u32 v2, v2, v0, s0
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; GFX942-NEXT: v_or_b32_e32 v3, 0x400000, v0
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; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
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; GFX942-NEXT: s_nop 1
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; GFX942-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
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; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
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; GFX942-NEXT: s_nop 1
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; GFX942-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc
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; GFX942-NEXT: v_bfe_u32 v2, v1, 16, 1
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; GFX942-NEXT: v_add3_u32 v2, v2, v1, s0
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; GFX942-NEXT: v_or_b32_e32 v3, 0x400000, v1
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; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
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; GFX942-NEXT: s_mov_b32 s0, 0x7060302
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; GFX942-NEXT: s_nop 0
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; GFX942-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
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; GFX942-NEXT: v_perm_b32 v0, v1, v0, s0
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; GFX942-NEXT: s_setpc_b64 s[30:31]
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%op = uitofp <2 x i1> %num to <2 x bfloat>
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ret <2 x bfloat> %op
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}
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define <3 x bfloat> @v_uitofp_v3i1_to_v3bf16(<3 x i1> %num) {
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; GFX942-LABEL: v_uitofp_v3i1_to_v3bf16:
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; GFX942: ; %bb.0:
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; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX942-NEXT: v_and_b32_e32 v2, 1, v2
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; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
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; GFX942-NEXT: s_movk_i32 s0, 0x7fff
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; GFX942-NEXT: v_and_b32_e32 v0, 1, v0
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; GFX942-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc
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; GFX942-NEXT: v_bfe_u32 v3, v2, 16, 1
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; GFX942-NEXT: v_add3_u32 v3, v3, v2, s0
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; GFX942-NEXT: v_or_b32_e32 v4, 0x400000, v2
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; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
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; GFX942-NEXT: v_and_b32_e32 v1, 1, v1
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; GFX942-NEXT: s_nop 0
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; GFX942-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
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; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; GFX942-NEXT: s_nop 1
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; GFX942-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
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; GFX942-NEXT: v_bfe_u32 v3, v0, 16, 1
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; GFX942-NEXT: v_add3_u32 v3, v3, v0, s0
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; GFX942-NEXT: v_or_b32_e32 v4, 0x400000, v0
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; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
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; GFX942-NEXT: s_nop 1
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; GFX942-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
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; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
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; GFX942-NEXT: s_nop 1
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; GFX942-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc
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; GFX942-NEXT: v_bfe_u32 v3, v1, 16, 1
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; GFX942-NEXT: v_add3_u32 v3, v3, v1, s0
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; GFX942-NEXT: v_or_b32_e32 v4, 0x400000, v1
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; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
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; GFX942-NEXT: s_mov_b32 s0, 0x7060302
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; GFX942-NEXT: s_nop 0
90+
; GFX942-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
91+
; GFX942-NEXT: v_perm_b32 v0, v1, v0, s0
92+
; GFX942-NEXT: v_alignbit_b32 v1, s0, v2, 16
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; GFX942-NEXT: s_setpc_b64 s[30:31]
94+
%op = uitofp <3 x i1> %num to <3 x bfloat>
95+
ret <3 x bfloat> %op
96+
}
97+
98+
define <4 x bfloat> @v_uitofp_v4i1_to_v4bf16(<4 x i1> %num) {
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; GFX942-LABEL: v_uitofp_v4i1_to_v4bf16:
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; GFX942: ; %bb.0:
101+
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX942-NEXT: v_and_b32_e32 v2, 1, v2
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; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
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; GFX942-NEXT: s_movk_i32 s0, 0x7fff
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; GFX942-NEXT: v_and_b32_e32 v3, 1, v3
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; GFX942-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc
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; GFX942-NEXT: v_bfe_u32 v4, v2, 16, 1
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; GFX942-NEXT: v_add3_u32 v4, v4, v2, s0
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; GFX942-NEXT: v_or_b32_e32 v5, 0x400000, v2
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; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
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; GFX942-NEXT: v_and_b32_e32 v0, 1, v0
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; GFX942-NEXT: v_and_b32_e32 v1, 1, v1
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; GFX942-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
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; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
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; GFX942-NEXT: s_nop 1
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; GFX942-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, vcc
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; GFX942-NEXT: v_bfe_u32 v4, v3, 16, 1
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; GFX942-NEXT: v_add3_u32 v4, v4, v3, s0
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; GFX942-NEXT: v_or_b32_e32 v5, 0x400000, v3
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; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
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; GFX942-NEXT: s_nop 1
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; GFX942-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
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; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; GFX942-NEXT: s_nop 1
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; GFX942-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
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; GFX942-NEXT: v_bfe_u32 v4, v0, 16, 1
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; GFX942-NEXT: v_add3_u32 v4, v4, v0, s0
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; GFX942-NEXT: v_or_b32_e32 v5, 0x400000, v0
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; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
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; GFX942-NEXT: s_nop 1
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; GFX942-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
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; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
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; GFX942-NEXT: s_nop 1
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; GFX942-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc
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; GFX942-NEXT: v_bfe_u32 v4, v1, 16, 1
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; GFX942-NEXT: v_add3_u32 v4, v4, v1, s0
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; GFX942-NEXT: v_or_b32_e32 v5, 0x400000, v1
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; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
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; GFX942-NEXT: s_mov_b32 s0, 0x7060302
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; GFX942-NEXT: s_nop 0
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; GFX942-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
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; GFX942-NEXT: v_perm_b32 v0, v1, v0, s0
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; GFX942-NEXT: v_perm_b32 v1, v3, v2, s0
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; GFX942-NEXT: s_setpc_b64 s[30:31]
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%op = uitofp <4 x i1> %num to <4 x bfloat>
146+
ret <4 x bfloat> %op
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}
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define bfloat @v_sitofp_i1_to_bf16(i1 %num) {
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; GFX942-LABEL: v_sitofp_i1_to_bf16:
151+
; GFX942: ; %bb.0:
152+
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX942-NEXT: v_and_b32_e32 v0, 1, v0
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; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; GFX942-NEXT: s_movk_i32 s0, 0x7fff
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; GFX942-NEXT: s_nop 0
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; GFX942-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc
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; GFX942-NEXT: v_bfe_u32 v1, v0, 16, 1
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; GFX942-NEXT: v_add3_u32 v1, v1, v0, s0
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; GFX942-NEXT: v_or_b32_e32 v2, 0x400000, v0
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; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
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; GFX942-NEXT: s_nop 1
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; GFX942-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
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; GFX942-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; GFX942-NEXT: s_setpc_b64 s[30:31]
166+
%op = sitofp i1 %num to bfloat
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ret bfloat %op
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}
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define <2 x bfloat> @v_sitofp_v2i1_to_v2bf16(<2 x i1> %num) {
171+
; GFX942-LABEL: v_sitofp_v2i1_to_v2bf16:
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; GFX942: ; %bb.0:
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; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX942-NEXT: v_and_b32_e32 v0, 1, v0
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; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; GFX942-NEXT: s_movk_i32 s0, 0x7fff
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; GFX942-NEXT: v_and_b32_e32 v1, 1, v1
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; GFX942-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc
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; GFX942-NEXT: v_bfe_u32 v2, v0, 16, 1
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; GFX942-NEXT: v_add3_u32 v2, v2, v0, s0
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; GFX942-NEXT: v_or_b32_e32 v3, 0x400000, v0
182+
; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
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; GFX942-NEXT: s_nop 1
184+
; GFX942-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
185+
; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
186+
; GFX942-NEXT: s_nop 1
187+
; GFX942-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc
188+
; GFX942-NEXT: v_bfe_u32 v2, v1, 16, 1
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; GFX942-NEXT: v_add3_u32 v2, v2, v1, s0
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; GFX942-NEXT: v_or_b32_e32 v3, 0x400000, v1
191+
; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
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; GFX942-NEXT: s_mov_b32 s0, 0x7060302
193+
; GFX942-NEXT: s_nop 0
194+
; GFX942-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
195+
; GFX942-NEXT: v_perm_b32 v0, v1, v0, s0
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; GFX942-NEXT: s_setpc_b64 s[30:31]
197+
%op = sitofp <2 x i1> %num to <2 x bfloat>
198+
ret <2 x bfloat> %op
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}
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define <3 x bfloat> @v_sitofp_v3i1_to_v3bf16(<3 x i1> %num) {
202+
; GFX942-LABEL: v_sitofp_v3i1_to_v3bf16:
203+
; GFX942: ; %bb.0:
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; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX942-NEXT: v_and_b32_e32 v2, 1, v2
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; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
207+
; GFX942-NEXT: s_movk_i32 s0, 0x7fff
208+
; GFX942-NEXT: v_and_b32_e32 v0, 1, v0
209+
; GFX942-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc
210+
; GFX942-NEXT: v_bfe_u32 v3, v2, 16, 1
211+
; GFX942-NEXT: v_add3_u32 v3, v3, v2, s0
212+
; GFX942-NEXT: v_or_b32_e32 v4, 0x400000, v2
213+
; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
214+
; GFX942-NEXT: v_and_b32_e32 v1, 1, v1
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; GFX942-NEXT: s_nop 0
216+
; GFX942-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
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; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; GFX942-NEXT: s_nop 1
219+
; GFX942-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc
220+
; GFX942-NEXT: v_bfe_u32 v3, v0, 16, 1
221+
; GFX942-NEXT: v_add3_u32 v3, v3, v0, s0
222+
; GFX942-NEXT: v_or_b32_e32 v4, 0x400000, v0
223+
; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
224+
; GFX942-NEXT: s_nop 1
225+
; GFX942-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
226+
; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
227+
; GFX942-NEXT: s_nop 1
228+
; GFX942-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc
229+
; GFX942-NEXT: v_bfe_u32 v3, v1, 16, 1
230+
; GFX942-NEXT: v_add3_u32 v3, v3, v1, s0
231+
; GFX942-NEXT: v_or_b32_e32 v4, 0x400000, v1
232+
; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
233+
; GFX942-NEXT: s_mov_b32 s0, 0x7060302
234+
; GFX942-NEXT: s_nop 0
235+
; GFX942-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
236+
; GFX942-NEXT: v_perm_b32 v0, v1, v0, s0
237+
; GFX942-NEXT: v_alignbit_b32 v1, s0, v2, 16
238+
; GFX942-NEXT: s_setpc_b64 s[30:31]
239+
%op = sitofp <3 x i1> %num to <3 x bfloat>
240+
ret <3 x bfloat> %op
241+
}
242+
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define <4 x bfloat> @v_sitofp_v4i1_to_v4bf16(<4 x i1> %num) {
244+
; GFX942-LABEL: v_sitofp_v4i1_to_v4bf16:
245+
; GFX942: ; %bb.0:
246+
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
247+
; GFX942-NEXT: v_and_b32_e32 v2, 1, v2
248+
; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
249+
; GFX942-NEXT: s_movk_i32 s0, 0x7fff
250+
; GFX942-NEXT: v_and_b32_e32 v3, 1, v3
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; GFX942-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc
252+
; GFX942-NEXT: v_bfe_u32 v4, v2, 16, 1
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; GFX942-NEXT: v_add3_u32 v4, v4, v2, s0
254+
; GFX942-NEXT: v_or_b32_e32 v5, 0x400000, v2
255+
; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
256+
; GFX942-NEXT: v_and_b32_e32 v0, 1, v0
257+
; GFX942-NEXT: v_and_b32_e32 v1, 1, v1
258+
; GFX942-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
259+
; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
260+
; GFX942-NEXT: s_nop 1
261+
; GFX942-NEXT: v_cndmask_b32_e64 v3, 0, -1.0, vcc
262+
; GFX942-NEXT: v_bfe_u32 v4, v3, 16, 1
263+
; GFX942-NEXT: v_add3_u32 v4, v4, v3, s0
264+
; GFX942-NEXT: v_or_b32_e32 v5, 0x400000, v3
265+
; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
266+
; GFX942-NEXT: s_nop 1
267+
; GFX942-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
268+
; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
269+
; GFX942-NEXT: s_nop 1
270+
; GFX942-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc
271+
; GFX942-NEXT: v_bfe_u32 v4, v0, 16, 1
272+
; GFX942-NEXT: v_add3_u32 v4, v4, v0, s0
273+
; GFX942-NEXT: v_or_b32_e32 v5, 0x400000, v0
274+
; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
275+
; GFX942-NEXT: s_nop 1
276+
; GFX942-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
277+
; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
278+
; GFX942-NEXT: s_nop 1
279+
; GFX942-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc
280+
; GFX942-NEXT: v_bfe_u32 v4, v1, 16, 1
281+
; GFX942-NEXT: v_add3_u32 v4, v4, v1, s0
282+
; GFX942-NEXT: v_or_b32_e32 v5, 0x400000, v1
283+
; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
284+
; GFX942-NEXT: s_mov_b32 s0, 0x7060302
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; GFX942-NEXT: s_nop 0
286+
; GFX942-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
287+
; GFX942-NEXT: v_perm_b32 v0, v1, v0, s0
288+
; GFX942-NEXT: v_perm_b32 v1, v3, v2, s0
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; GFX942-NEXT: s_setpc_b64 s[30:31]
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%op = sitofp <4 x i1> %num to <4 x bfloat>
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ret <4 x bfloat> %op
292+
}

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