Skip to content

Commit b856e77

Browse files
jyknightjyknight
authored
Set MaxAtomicSizeInBitsSupported for remaining targets. (#75703)
Targets affected: - NVPTX and BPF: set to 64 bits. - ARC, Lanai, and MSP430: set to 0 (they don't implement atomics). Those which didn't yet add AtomicExpandPass to their pass pipeline now do so. This will result in larger atomic operations getting expanded to `__atomic_*` libcalls via AtomicExpandPass. On all these targets, this now matches what Clang already does in the frontend. The only targets which do not configure AtomicExpandPass now are: - DirectX and SPIRV: they aren't normal backends. - AVR: a single-cpu architecture with no privileged/user divide, which could implement all atomics by disabling/enabling interrupts, regardless of size/alignment. Will be addressed by future work.
1 parent 96c4f10 commit b856e77

14 files changed

+101
-22
lines changed

‎llvm/lib/Target/ARC/ARCISelLowering.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -174,6 +174,8 @@ ARCTargetLowering::ARCTargetLowering(const TargetMachine &TM,
174174
setOperationAction(ISD::READCYCLECOUNTER, MVT::i32, Legal);
175175
setOperationAction(ISD::READCYCLECOUNTER, MVT::i64,
176176
isTypeLegal(MVT::i64) ? Legal : Custom);
177+
178+
setMaxAtomicSizeInBitsSupported(0);
177179
}
178180

179181
const char *ARCTargetLowering::getTargetNodeName(unsigned Opcode) const {

‎llvm/lib/Target/ARC/ARCTargetMachine.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,7 @@ class ARCPassConfig : public TargetPassConfig {
5757
return getTM<ARCTargetMachine>();
5858
}
5959

60+
void addIRPasses() override;
6061
bool addInstSelector() override;
6162
void addPreEmitPass() override;
6263
void addPreRegAlloc() override;
@@ -68,6 +69,12 @@ TargetPassConfig *ARCTargetMachine::createPassConfig(PassManagerBase &PM) {
6869
return new ARCPassConfig(*this, PM);
6970
}
7071

72+
void ARCPassConfig::addIRPasses() {
73+
addPass(createAtomicExpandPass());
74+
75+
TargetPassConfig::addIRPasses();
76+
}
77+
7178
bool ARCPassConfig::addInstSelector() {
7279
addPass(createARCISelDag(getARCTargetMachine(), getOptLevel()));
7380
return false;

‎llvm/lib/Target/BPF/BPFISelLowering.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -151,6 +151,7 @@ BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
151151
}
152152

153153
setBooleanContents(ZeroOrOneBooleanContent);
154+
setMaxAtomicSizeInBitsSupported(64);
154155

155156
// Function alignments
156157
setMinFunctionAlignment(Align(8));

‎llvm/lib/Target/BPF/BPFTargetMachine.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,9 @@ void BPFTargetMachine::registerPassBuilderCallbacks(
149149
}
150150

151151
void BPFPassConfig::addIRPasses() {
152+
addPass(createAtomicExpandPass());
152153
addPass(createBPFCheckAndAdjustIR());
154+
153155
TargetPassConfig::addIRPasses();
154156
}
155157

‎llvm/lib/Target/Lanai/LanaiISelLowering.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -166,6 +166,8 @@ LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
166166

167167
// Booleans always contain 0 or 1.
168168
setBooleanContents(ZeroOrOneBooleanContent);
169+
170+
setMaxAtomicSizeInBitsSupported(0);
169171
}
170172

171173
SDValue LanaiTargetLowering::LowerOperation(SDValue Op,

‎llvm/lib/Target/Lanai/LanaiTargetMachine.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -93,6 +93,7 @@ class LanaiPassConfig : public TargetPassConfig {
9393
return getTM<LanaiTargetMachine>();
9494
}
9595

96+
void addIRPasses() override;
9697
bool addInstSelector() override;
9798
void addPreSched2() override;
9899
void addPreEmitPass() override;
@@ -104,6 +105,12 @@ LanaiTargetMachine::createPassConfig(PassManagerBase &PassManager) {
104105
return new LanaiPassConfig(*this, &PassManager);
105106
}
106107

108+
void LanaiPassConfig::addIRPasses() {
109+
addPass(createAtomicExpandPass());
110+
111+
TargetPassConfig::addIRPasses();
112+
}
113+
107114
// Install an instruction selector pass.
108115
bool LanaiPassConfig::addInstSelector() {
109116
addPass(createLanaiISelDag(getLanaiTargetMachine()));

‎llvm/lib/Target/MSP430/MSP430ISelLowering.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -333,6 +333,7 @@ MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
333333

334334
setMinFunctionAlignment(Align(2));
335335
setPrefFunctionAlignment(Align(2));
336+
setMaxAtomicSizeInBitsSupported(0);
336337
}
337338

338339
SDValue MSP430TargetLowering::LowerOperation(SDValue Op,

‎llvm/lib/Target/MSP430/MSP430TargetMachine.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -65,6 +65,7 @@ class MSP430PassConfig : public TargetPassConfig {
6565
return getTM<MSP430TargetMachine>();
6666
}
6767

68+
void addIRPasses() override;
6869
bool addInstSelector() override;
6970
void addPreEmitPass() override;
7071
};
@@ -81,6 +82,12 @@ MachineFunctionInfo *MSP430TargetMachine::createMachineFunctionInfo(
8182
F, STI);
8283
}
8384

85+
void MSP430PassConfig::addIRPasses() {
86+
addPass(createAtomicExpandPass());
87+
88+
TargetPassConfig::addIRPasses();
89+
}
90+
8491
bool MSP430PassConfig::addInstSelector() {
8592
// Install an instruction selector.
8693
addPass(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));

‎llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -854,6 +854,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
854854
computeRegisterProperties(STI.getRegisterInfo());
855855

856856
setMinCmpXchgSizeInBits(32);
857+
setMaxAtomicSizeInBitsSupported(64);
857858
}
858859

859860
const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {

‎llvm/test/CodeGen/ARC/atomic-oversize.ll

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
; RUN: llc -mtriple=arc < %s | FileCheck %s
2+
3+
; Native atomics are unsupported, so all are oversize.
4+
define void @test(ptr %a) nounwind {
5+
; CHECK-LABEL: test:
6+
; CHECK: bl @__atomic_load_1
7+
; CHECK: bl @__atomic_store_1
8+
%1 = load atomic i8, ptr %a seq_cst, align 16
9+
store atomic i8 %1, ptr %a seq_cst, align 16
10+
ret void
11+
}

‎llvm/test/CodeGen/BPF/atomic-oversize.ll

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
; RUN: llc -mtriple=bpf < %s | FileCheck %s
2+
; XFAIL: *
3+
; Doesn't currently build, with error 'only small returns supported'.
4+
5+
define void @test(ptr %a) nounwind {
6+
; CHECK-LABEL: test:
7+
; CHECK: call __atomic_load_16
8+
; CHECK: call __atomic_store_16
9+
%1 = load atomic i128, ptr %a monotonic, align 16
10+
store atomic i128 %1, ptr %a monotonic, align 16
11+
ret void
12+
}

‎llvm/test/CodeGen/Lanai/atomic-oversize.ll

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
; RUN: llc -mtriple=lanai < %s | FileCheck %s
2+
3+
; Native atomics are unsupported, so all are oversize.
4+
define void @test(ptr %a) nounwind {
5+
; CHECK-LABEL: test:
6+
; CHECK: bt __atomic_load_1
7+
; CHECK: bt __atomic_store_1
8+
%1 = load atomic i8, ptr %a monotonic, align 16
9+
store atomic i8 %1, ptr %a monotonic, align 16
10+
ret void
11+
}

‎llvm/test/CodeGen/MSP430/atomic-oversize.ll

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
; RUN: llc -mtriple=msp430 < %s | FileCheck %s
2+
3+
; Native atomics are unsupported, so all are oversize.
4+
define void @test(ptr %a) nounwind {
5+
; CHECK-LABEL: test:
6+
; CHECK: call #__atomic_load_1
7+
; CHECK: call #__atomic_store_1
8+
%1 = load atomic i8, ptr %a monotonic, align 16
9+
store atomic i8 %1, ptr %a monotonic, align 16
10+
ret void
11+
}

‎llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll

Lines changed: 26 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -140,26 +140,30 @@ entry:
140140
ret void
141141
}
142142

143-
; TODO: We might still want to test other types, such as i128. Currently the
144-
; backend doesn't support them. Atomic expand only supports expansion to cas of
145-
; the same bitwidth, which means even after expansion, the back end still
146-
; doesn't support the instruction. Here we still put the tests. Remove the
147-
; comment once we have proper support, either from atomic expand or backend.
148-
149-
; define void @bitwise_i128(ptr %0, i128 %1) {
150-
; entry:
151-
; %2 = atomicrmw and ptr %0, i128 %1 monotonic, align 16
152-
; %3 = atomicrmw or ptr %0, i128 %1 monotonic, align 16
153-
; %4 = atomicrmw xor ptr %0, i128 %1 monotonic, align 16
154-
; %5 = atomicrmw xchg ptr %0, i128 %1 monotonic, align 16
155-
; ret void
156-
; }
143+
; CHECK-LABEL: bitwise_i128
144+
define void @bitwise_i128(ptr %0, i128 %1) {
145+
entry:
146+
; ALL: __atomic_fetch_and_16
147+
%2 = atomicrmw and ptr %0, i128 %1 monotonic, align 16
148+
; ALL: __atomic_fetch_or_16
149+
%3 = atomicrmw or ptr %0, i128 %1 monotonic, align 16
150+
; ALL: __atomic_fetch_xor_16
151+
%4 = atomicrmw xor ptr %0, i128 %1 monotonic, align 16
152+
; ALL: __atomic_exchange_16
153+
%5 = atomicrmw xchg ptr %0, i128 %1 monotonic, align 16
154+
ret void
155+
}
157156

158-
; define void @minmax_i128(ptr %0, i128 %1) {
159-
; entry:
160-
; %2 = atomicrmw min ptr %0, i128 %1 monotonic, align 16
161-
; %3 = atomicrmw max ptr %0, i128 %1 monotonic, align 16
162-
; %4 = atomicrmw umin ptr %0, i128 %1 monotonic, align 16
163-
; %5 = atomicrmw umax ptr %0, i128 %1 monotonic, align 16
164-
; ret void
165-
; }
157+
; CHECK-LABEL: minmax_i128
158+
define void @minmax_i128(ptr %0, i128 %1) {
159+
entry:
160+
; ALL: __atomic_compare_exchange_16
161+
%2 = atomicrmw min ptr %0, i128 %1 monotonic, align 16
162+
; ALL: __atomic_compare_exchange_16
163+
%3 = atomicrmw max ptr %0, i128 %1 monotonic, align 16
164+
; ALL: __atomic_compare_exchange_16
165+
%4 = atomicrmw umin ptr %0, i128 %1 monotonic, align 16
166+
; ALL: __atomic_compare_exchange_16
167+
%5 = atomicrmw umax ptr %0, i128 %1 monotonic, align 16
168+
ret void
169+
}

0 commit comments

Comments
 (0)