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[RISCV] Split PseudoVFRSQRT7 and PseudoVFREC7 by SEW
Co-authored-by: Wang Pengcheng <[email protected]>
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-33
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4 files changed

+52
-33
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‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 37 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -2577,29 +2577,33 @@ multiclass VPseudoVSQR_V_RM {
25772577
multiclass VPseudoVRCP_V {
25782578
foreach m = MxListF in {
25792579
defvar mx = m.MX;
2580-
let VLMul = m.value in {
2581-
def "_V_" # mx
2582-
: VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
2583-
SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, forceMergeOpRead=true>;
2584-
def "_V_" # mx # "_MASK"
2585-
: VPseudoUnaryMask<m.vrclass, m.vrclass>,
2586-
RISCVMaskedPseudo<MaskIdx = 2>,
2587-
SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, forceMergeOpRead=true>;
2580+
foreach e = SchedSEWSet<mx, isF=1>.val in {
2581+
let VLMul = m.value in {
2582+
def "_V_" # mx # "_E" # e
2583+
: VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
2584+
SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, e, forceMergeOpRead=true>;
2585+
def "_V_" # mx # "_E" # e # "_MASK"
2586+
: VPseudoUnaryMask<m.vrclass, m.vrclass>,
2587+
RISCVMaskedPseudo<MaskIdx = 2>,
2588+
SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, e, forceMergeOpRead=true>;
2589+
}
25882590
}
25892591
}
25902592
}
25912593

25922594
multiclass VPseudoVRCP_V_RM {
25932595
foreach m = MxListF in {
25942596
defvar mx = m.MX;
2595-
let VLMul = m.value in {
2596-
def "_V_" # mx
2597-
: VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.vrclass>,
2598-
SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, forceMergeOpRead=true>;
2599-
def "_V_" # mx # "_MASK"
2600-
: VPseudoUnaryMaskRoundingMode<m.vrclass, m.vrclass>,
2601-
RISCVMaskedPseudo<MaskIdx = 2>,
2602-
SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, forceMergeOpRead=true>;
2597+
foreach e = SchedSEWSet<mx, isF=1>.val in {
2598+
let VLMul = m.value in {
2599+
def "_V_" # mx # "_E" # e
2600+
: VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.vrclass>,
2601+
SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, e, forceMergeOpRead=true>;
2602+
def "_V_" # mx # "_E" # e # "_MASK"
2603+
: VPseudoUnaryMaskRoundingMode<m.vrclass, m.vrclass>,
2604+
RISCVMaskedPseudo<MaskIdx = 2>,
2605+
SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, e, forceMergeOpRead=true>;
2606+
}
26032607
}
26042608
}
26052609
}
@@ -3939,12 +3943,16 @@ class VPatUnaryNoMask<string intrinsic_name,
39393943
int log2sew,
39403944
LMULInfo vlmul,
39413945
VReg result_reg_class,
3942-
VReg op2_reg_class> :
3946+
VReg op2_reg_class,
3947+
bit isSEWAware = 0> :
39433948
Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
39443949
(result_type result_reg_class:$merge),
39453950
(op2_type op2_reg_class:$rs2),
39463951
VLOpFrag)),
3947-
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
3952+
(!cast<Instruction>(
3953+
!if(isSEWAware,
3954+
inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew),
3955+
inst#"_"#kind#"_"#vlmul.MX))
39483956
(result_type result_reg_class:$merge),
39493957
(op2_type op2_reg_class:$rs2),
39503958
GPR:$vl, log2sew, TU_MU)>;
@@ -3983,13 +3991,17 @@ class VPatUnaryMask<string intrinsic_name,
39833991
int log2sew,
39843992
LMULInfo vlmul,
39853993
VReg result_reg_class,
3986-
VReg op2_reg_class> :
3994+
VReg op2_reg_class,
3995+
bit isSEWAware = 0> :
39873996
Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")
39883997
(result_type result_reg_class:$merge),
39893998
(op2_type op2_reg_class:$rs2),
39903999
(mask_type V0),
39914000
VLOpFrag, (XLenVT timm:$policy))),
3992-
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_MASK")
4001+
(!cast<Instruction>(
4002+
!if(isSEWAware,
4003+
inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",
4004+
inst#"_"#kind#"_"#vlmul.MX#"_MASK"))
39934005
(result_type result_reg_class:$merge),
39944006
(op2_type op2_reg_class:$rs2),
39954007
(mask_type V0), GPR:$vl, log2sew, (XLenVT timm:$policy))>;
@@ -4681,15 +4693,15 @@ multiclass VPatUnaryV_VF<string intrinsic, string instruction, string suffix,
46814693
}
46824694

46834695
multiclass VPatUnaryV_V<string intrinsic, string instruction,
4684-
list<VTypeInfo> vtilist> {
4696+
list<VTypeInfo> vtilist, bit isSEWAware = 0> {
46854697
foreach vti = vtilist in {
46864698
let Predicates = GetVTypePredicates<vti>.Predicates in {
46874699
def : VPatUnaryNoMask<intrinsic, instruction, "V",
46884700
vti.Vector, vti.Vector, vti.Log2SEW,
4689-
vti.LMul, vti.RegClass, vti.RegClass>;
4701+
vti.LMul, vti.RegClass, vti.RegClass, isSEWAware>;
46904702
def : VPatUnaryMask<intrinsic, instruction, "V",
46914703
vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
4692-
vti.LMul, vti.RegClass, vti.RegClass>;
4704+
vti.LMul, vti.RegClass, vti.RegClass, isSEWAware>;
46934705
}
46944706
}
46954707
}
@@ -7175,12 +7187,12 @@ defm : VPatUnaryV_V_RM<"int_riscv_vfsqrt", "PseudoVFSQRT", AllFloatVectors, isSE
71757187
//===----------------------------------------------------------------------===//
71767188
// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
71777189
//===----------------------------------------------------------------------===//
7178-
defm : VPatUnaryV_V<"int_riscv_vfrsqrt7", "PseudoVFRSQRT7", AllFloatVectors>;
7190+
defm : VPatUnaryV_V<"int_riscv_vfrsqrt7", "PseudoVFRSQRT7", AllFloatVectors, isSEWAware=1>;
71797191

71807192
//===----------------------------------------------------------------------===//
71817193
// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
71827194
//===----------------------------------------------------------------------===//
7183-
defm : VPatUnaryV_V_RM<"int_riscv_vfrec7", "PseudoVFREC7", AllFloatVectors>;
7195+
defm : VPatUnaryV_V_RM<"int_riscv_vfrec7", "PseudoVFREC7", AllFloatVectors, isSEWAware=1>;
71847196

71857197
//===----------------------------------------------------------------------===//
71867198
// 13.11. Vector Floating-Point Min/Max Instructions

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -743,14 +743,14 @@ foreach mx = SchedMxListF in {
743743
defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
744744
defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
745745
defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
746+
defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
746747
}
747748
}
748749
}
749750
foreach mx = SchedMxList in {
750751
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
751752
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
752753
let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
753-
defm "" : LMULWriteResMX<"WriteVFRecpV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
754754
defm "" : LMULWriteResMX<"WriteVFCvtIToFV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
755755
defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
756756
}
@@ -1168,7 +1168,7 @@ defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>;
11681168
defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>;
11691169
defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>;
11701170
defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;
1171-
defm "" : LMULReadAdvance<"ReadVFRecpV", 0>;
1171+
defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>;
11721172
defm "" : LMULReadAdvance<"ReadVFMinMaxV", 0>;
11731173
defm "" : LMULReadAdvance<"ReadVFMinMaxF", 0>;
11741174
defm "" : LMULReadAdvance<"ReadVFSgnjV", 0>;

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -510,6 +510,14 @@ foreach mx = SchedMxListF in {
510510
}
511511
}
512512
}
513+
foreach mx = SchedMxListF in {
514+
foreach sew = SchedSEWSet<mx, isF=1>.val in {
515+
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
516+
defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
517+
let Latency = 2, ReleaseAtCycles = [LMulLat] in
518+
defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
519+
}
520+
}
513521
foreach mx = SchedMxList in {
514522
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
515523
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
@@ -520,7 +528,6 @@ foreach mx = SchedMxList in {
520528
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
521529
defm "" : LMULWriteResMX<"WriteVFCmpV", [SiFiveP600VectorArith], mx, IsWorstCase>;
522530
defm "" : LMULWriteResMX<"WriteVFCmpF", [SiFiveP600VectorArith], mx, IsWorstCase>;
523-
defm "" : LMULWriteResMX<"WriteVFRecpV", [SiFiveP600VectorArith], mx, IsWorstCase>;
524531
}
525532
let Latency = 1, ReleaseAtCycles = [LMulLat] in {
526533
defm "" : LMULWriteResMX<"WriteVFSgnjV", [SiFiveP600VectorArith], mx, IsWorstCase>;
@@ -958,7 +965,7 @@ defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>;
958965
defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>;
959966
defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>;
960967
defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;
961-
defm "" : LMULReadAdvance<"ReadVFRecpV", 0>;
968+
defm "" : LMULSEWReadAdvance<"ReadVFRecpV", 0>;
962969
defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;
963970
defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;
964971
defm "" : LMULReadAdvance<"ReadVFMinMaxV", 0>;

‎llvm/lib/Target/RISCV/RISCVScheduleV.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -432,7 +432,7 @@ defm "" : LMULSEWSchedWritesFW<"WriteVFWMulAddF">;
432432
defm "" : LMULSEWSchedWritesF<"WriteVFSqrtV">;
433433
// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
434434
// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
435-
defm "" : LMULSchedWrites<"WriteVFRecpV">;
435+
defm "" : LMULSEWSchedWritesF<"WriteVFRecpV">;
436436
// 13.11. Vector Floating-Point MIN/MAX Instructions
437437
defm "" : LMULSchedWrites<"WriteVFMinMaxV">;
438438
defm "" : LMULSchedWrites<"WriteVFMinMaxF">;
@@ -657,7 +657,7 @@ defm "" : LMULSEWSchedReadsFW<"ReadVFWMulAddF">;
657657
defm "" : LMULSEWSchedReadsF<"ReadVFSqrtV">;
658658
// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
659659
// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
660-
defm "" : LMULSchedReads<"ReadVFRecpV">;
660+
defm "" : LMULSEWSchedReadsF<"ReadVFRecpV">;
661661
// 13.11. Vector Floating-Point MIN/MAX Instructions
662662
defm "" : LMULSchedReads<"ReadVFMinMaxV">;
663663
defm "" : LMULSchedReads<"ReadVFMinMaxF">;
@@ -895,7 +895,7 @@ defm "" : LMULSEWWriteResF<"WriteVFMulAddF", []>;
895895
defm "" : LMULSEWWriteResFW<"WriteVFWMulAddV", []>;
896896
defm "" : LMULSEWWriteResFW<"WriteVFWMulAddF", []>;
897897
defm "" : LMULSEWWriteResF<"WriteVFSqrtV", []>;
898-
defm "" : LMULWriteRes<"WriteVFRecpV", []>;
898+
defm "" : LMULSEWWriteResF<"WriteVFRecpV", []>;
899899
defm "" : LMULWriteRes<"WriteVFMinMaxV", []>;
900900
defm "" : LMULWriteRes<"WriteVFMinMaxF", []>;
901901
defm "" : LMULWriteRes<"WriteVFSgnjV", []>;
@@ -1051,7 +1051,7 @@ defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>;
10511051
defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>;
10521052
defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>;
10531053
defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;
1054-
defm "" : LMULReadAdvance<"ReadVFRecpV", 0>;
1054+
defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>;
10551055
defm "" : LMULReadAdvance<"ReadVFMinMaxV", 0>;
10561056
defm "" : LMULReadAdvance<"ReadVFMinMaxF", 0>;
10571057
defm "" : LMULReadAdvance<"ReadVFSgnjV", 0>;

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