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Mel-ChenMel-Chen
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[LoopVectorize] Vectorize fixed-order recurrence with vscale x 1. (#142772)
When the fixed-order recurrence phi is live-out from the loop, the vectorizer uses VPInstruction::ExtractPenultimateElement to extract the penultimate element from the recurrence vector. However, this is not feasible when the VF is vscale x 1, since vscale could be 1, making the vector contain only one element. This patch changes the behavior for vscale x 1 by extracting the last element from the vector produced by splicing the recurrence phi and the previous value. This ensures we can still determine the correct live-out value of the recurrence phi.
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4 files changed

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-42
lines changed

4 files changed

+130
-42
lines changed

‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -6163,11 +6163,6 @@ LoopVectorizationCostModel::getInstructionCost(Instruction *I,
61636163

61646164
// First-order recurrences are replaced by vector shuffles inside the loop.
61656165
if (VF.isVector() && Legal->isFixedOrderRecurrence(Phi)) {
6166-
// For <vscale x 1 x i64>, if vscale = 1 we are unable to extract the
6167-
// penultimate value of the recurrence.
6168-
// TODO: Consider vscale_range info.
6169-
if (VF.isScalable() && VF.getKnownMinValue() == 1)
6170-
return InstructionCost::getInvalid();
61716166
SmallVector<int> Mask(VF.getKnownMinValue());
61726167
std::iota(Mask.begin(), Mask.end(), VF.getKnownMinValue() - 1);
61736168
return TTI.getShuffleCost(TargetTransformInfo::SK_Splice,
@@ -8556,13 +8551,17 @@ addUsersInExitBlocks(VPlan &Plan,
85568551
/// users in the original exit block using the VPIRInstruction wrapping to the
85578552
/// LCSSA phi.
85588553
static void addExitUsersForFirstOrderRecurrences(
8559-
VPlan &Plan, SetVector<VPIRInstruction *> &ExitUsersToFix) {
8554+
VPlan &Plan, SetVector<VPIRInstruction *> &ExitUsersToFix, VFRange &Range) {
85608555
VPRegionBlock *VectorRegion = Plan.getVectorLoopRegion();
85618556
auto *ScalarPHVPBB = Plan.getScalarPreheader();
85628557
auto *MiddleVPBB = Plan.getMiddleBlock();
85638558
VPBuilder ScalarPHBuilder(ScalarPHVPBB);
85648559
VPBuilder MiddleBuilder(MiddleVPBB, MiddleVPBB->getFirstNonPhi());
85658560

8561+
auto IsScalableOne = [](ElementCount VF) -> bool {
8562+
return VF == ElementCount::getScalable(1);
8563+
};
8564+
85668565
for (auto &HeaderPhi : VectorRegion->getEntryBasicBlock()->phis()) {
85678566
auto *FOR = dyn_cast<VPFirstOrderRecurrencePHIRecipe>(&HeaderPhi);
85688567
if (!FOR)
@@ -8644,6 +8643,15 @@ static void addExitUsersForFirstOrderRecurrences(
86448643
for (VPIRInstruction *ExitIRI : ExitUsersToFix) {
86458644
if (ExitIRI->getOperand(0) != FOR)
86468645
continue;
8646+
// For VF vscale x 1, if vscale = 1, we are unable to extract the
8647+
// penultimate value of the recurrence. Instead, we rely on function
8648+
// addUsersInExitBlocks to extract the last element from the result of
8649+
// VPInstruction::FirstOrderRecurrenceSplice by leaving the user of the
8650+
// recurrence phi in ExitUsersToFix.
8651+
// TODO: Consider vscale_range info and UF.
8652+
if (LoopVectorizationPlanner::getDecisionAndClampRange(IsScalableOne,
8653+
Range))
8654+
return;
86478655
VPValue *PenultimateElement = MiddleBuilder.createNaryOp(
86488656
VPInstruction::ExtractPenultimateElement, {FOR->getBackedgeValue()},
86498657
{}, "vector.recur.extract.for.phi");
@@ -8858,7 +8866,7 @@ VPlanPtr LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes(
88588866
addScalarResumePhis(RecipeBuilder, *Plan, IVEndValues);
88598867
SetVector<VPIRInstruction *> ExitUsersToFix =
88608868
collectUsersInLatchExitBlock(*Plan);
8861-
addExitUsersForFirstOrderRecurrences(*Plan, ExitUsersToFix);
8869+
addExitUsersForFirstOrderRecurrences(*Plan, ExitUsersToFix, Range);
88628870
addUsersInExitBlocks(*Plan, ExitUsersToFix);
88638871

88648872
// ---------------------------------------------------------------------------

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3680,9 +3680,6 @@ VPFirstOrderRecurrencePHIRecipe::computeCost(ElementCount VF,
36803680
if (VF.isScalar())
36813681
return Ctx.TTI.getCFInstrCost(Instruction::PHI, Ctx.CostKind);
36823682

3683-
if (VF == ElementCount::getScalable(1))
3684-
return InstructionCost::getInvalid();
3685-
36863683
return 0;
36873684
}
36883685

‎llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll

Lines changed: 32 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -1,56 +1,63 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2-
; RUN: opt -p loop-vectorize -S %s | FileCheck %s
2+
; RUN: opt -p loop-vectorize -scalable-vectorization=on -S %s | FileCheck %s
33

44
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
55
target triple = "riscv64-unknown-linux-gnu"
66

7-
; Make sure we do not pick <vscale x 1 x i64> as VF for a loop with a
8-
; first-order recurrence.
97
define i64 @pr97452_scalable_vf1_for(ptr %src, ptr noalias %dst) #0 {
108
; CHECK-LABEL: define i64 @pr97452_scalable_vf1_for(
119
; CHECK-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR0:[0-9]+]] {
1210
; CHECK-NEXT: [[ENTRY:.*]]:
13-
; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
11+
; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
12+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 23, [[TMP0]]
13+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
1414
; CHECK: [[VECTOR_PH]]:
15+
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
16+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 23, [[TMP1]]
17+
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 23, [[N_MOD_VF]]
18+
; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
19+
; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vscale.i32()
20+
; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP3]], 1
21+
; CHECK-NEXT: [[VECTOR_RECUR_INIT:%.*]] = insertelement <vscale x 1 x i64> poison, i64 0, i32 [[TMP4]]
1522
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
1623
; CHECK: [[VECTOR_BODY]]:
1724
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
18-
; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <4 x i64> [ <i64 poison, i64 poison, i64 poison, i64 0>, %[[VECTOR_PH]] ], [ [[WIDE_LOAD1:%.*]], %[[VECTOR_BODY]] ]
19-
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[INDEX]]
20-
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP2]], i32 0
21-
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP2]], i32 4
22-
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP1]], align 8
23-
; CHECK-NEXT: [[WIDE_LOAD1]] = load <4 x i64>, ptr [[TMP5]], align 8
24-
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i64> [[VECTOR_RECUR]], <4 x i64> [[WIDE_LOAD]], <4 x i32> <i32 3, i32 4, i32 5, i32 6>
25-
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i64> [[WIDE_LOAD]], <4 x i64> [[WIDE_LOAD1]], <4 x i32> <i32 3, i32 4, i32 5, i32 6>
25+
; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <vscale x 1 x i64> [ [[VECTOR_RECUR_INIT]], %[[VECTOR_PH]] ], [ [[WIDE_LOAD:%.*]], %[[VECTOR_BODY]] ]
26+
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[INDEX]]
27+
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP5]], i32 0
28+
; CHECK-NEXT: [[WIDE_LOAD]] = load <vscale x 1 x i64>, ptr [[TMP6]], align 8
29+
; CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 1 x i64> @llvm.vector.splice.nxv1i64(<vscale x 1 x i64> [[VECTOR_RECUR]], <vscale x 1 x i64> [[WIDE_LOAD]], i32 -1)
2630
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[INDEX]]
2731
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[TMP8]], i32 0
28-
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP8]], i32 4
29-
; CHECK-NEXT: store <4 x i64> [[TMP3]], ptr [[TMP9]], align 8
30-
; CHECK-NEXT: store <4 x i64> [[TMP4]], ptr [[TMP7]], align 8
31-
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
32-
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16
33-
; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
32+
; CHECK-NEXT: store <vscale x 1 x i64> [[TMP7]], ptr [[TMP9]], align 8
33+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP2]]
34+
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
35+
; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
3436
; CHECK: [[MIDDLE_BLOCK]]:
35-
; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i64> [[WIDE_LOAD1]], i32 2
36-
; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i64> [[WIDE_LOAD1]], i32 3
37-
; CHECK-NEXT: br i1 false, label %[[EXIT:.*]], label %[[SCALAR_PH]]
37+
; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.vscale.i32()
38+
; CHECK-NEXT: [[TMP12:%.*]] = sub i32 [[TMP11]], 1
39+
; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x i64> [[TMP7]], i32 [[TMP12]]
40+
; CHECK-NEXT: [[TMP14:%.*]] = call i32 @llvm.vscale.i32()
41+
; CHECK-NEXT: [[TMP15:%.*]] = sub i32 [[TMP14]], 1
42+
; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <vscale x 1 x i64> [[WIDE_LOAD]], i32 [[TMP15]]
43+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 23, [[N_VEC]]
44+
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
3845
; CHECK: [[SCALAR_PH]]:
3946
; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
40-
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 16, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
47+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
4148
; CHECK-NEXT: br label %[[LOOP:.*]]
4249
; CHECK: [[LOOP]]:
4350
; CHECK-NEXT: [[FOR:%.*]] = phi i64 [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[L:%.*]], %[[LOOP]] ]
4451
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
4552
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
46-
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[IV]]
47-
; CHECK-NEXT: [[L]] = load i64, ptr [[GEP]], align 8
53+
; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[IV]]
54+
; CHECK-NEXT: [[L]] = load i64, ptr [[GEP_SRC]], align 8
4855
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[IV]]
4956
; CHECK-NEXT: store i64 [[FOR]], ptr [[GEP_DST]], align 8
5057
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 22
5158
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
5259
; CHECK: [[EXIT]]:
53-
; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[FOR]], %[[LOOP]] ], [ [[VECTOR_RECUR_EXTRACT_FOR_PHI]], %[[MIDDLE_BLOCK]] ]
60+
; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[FOR]], %[[LOOP]] ], [ [[TMP13]], %[[MIDDLE_BLOCK]] ]
5461
; CHECK-NEXT: ret i64 [[RES]]
5562
;
5663
entry:

‎llvm/test/Transforms/LoopVectorize/first-order-recurrence-scalable-vf1.ll

Lines changed: 83 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -8,17 +8,51 @@ define i64 @pr97452_scalable_vf1_for_live_out(ptr %src) {
88
; CHECK-LABEL: define i64 @pr97452_scalable_vf1_for_live_out(
99
; CHECK-SAME: ptr [[SRC:%.*]]) {
1010
; CHECK-NEXT: [[ENTRY:.*]]:
11+
; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
12+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 23, [[TMP0]]
13+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
14+
; CHECK: [[VECTOR_PH]]:
15+
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
16+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 23, [[TMP1]]
17+
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 23, [[N_MOD_VF]]
18+
; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
19+
; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vscale.i32()
20+
; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP3]], 1
21+
; CHECK-NEXT: [[VECTOR_RECUR_INIT:%.*]] = insertelement <vscale x 1 x i64> poison, i64 0, i32 [[TMP4]]
22+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
23+
; CHECK: [[VECTOR_BODY]]:
24+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
25+
; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <vscale x 1 x i64> [ [[VECTOR_RECUR_INIT]], %[[VECTOR_PH]] ], [ [[WIDE_LOAD:%.*]], %[[VECTOR_BODY]] ]
26+
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[INDEX]]
27+
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP5]], i32 0
28+
; CHECK-NEXT: [[WIDE_LOAD]] = load <vscale x 1 x i64>, ptr [[TMP6]], align 8
29+
; CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 1 x i64> @llvm.vector.splice.nxv1i64(<vscale x 1 x i64> [[VECTOR_RECUR]], <vscale x 1 x i64> [[WIDE_LOAD]], i32 -1)
30+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP2]]
31+
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
32+
; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
33+
; CHECK: [[MIDDLE_BLOCK]]:
34+
; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.vscale.i32()
35+
; CHECK-NEXT: [[TMP10:%.*]] = sub i32 [[TMP9]], 1
36+
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x i64> [[TMP7]], i32 [[TMP10]]
37+
; CHECK-NEXT: [[TMP12:%.*]] = call i32 @llvm.vscale.i32()
38+
; CHECK-NEXT: [[TMP13:%.*]] = sub i32 [[TMP12]], 1
39+
; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <vscale x 1 x i64> [[WIDE_LOAD]], i32 [[TMP13]]
40+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 23, [[N_VEC]]
41+
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
42+
; CHECK: [[SCALAR_PH]]:
43+
; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
44+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
1145
; CHECK-NEXT: br label %[[LOOP:.*]]
1246
; CHECK: [[LOOP]]:
13-
; CHECK-NEXT: [[FOR:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[L:%.*]], %[[LOOP]] ]
14-
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
47+
; CHECK-NEXT: [[FOR:%.*]] = phi i64 [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[L:%.*]], %[[LOOP]] ]
48+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
1549
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
1650
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[IV]]
1751
; CHECK-NEXT: [[L]] = load i64, ptr [[GEP]], align 8
1852
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 22
19-
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]
53+
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
2054
; CHECK: [[EXIT]]:
21-
; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[FOR]], %[[LOOP]] ]
55+
; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[FOR]], %[[LOOP]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ]
2256
; CHECK-NEXT: ret i64 [[RES]]
2357
;
2458
entry:
@@ -43,17 +77,51 @@ define void @pr97452_scalable_vf1_for_no_live_out(ptr %src, ptr noalias %dst) {
4377
; CHECK-LABEL: define void @pr97452_scalable_vf1_for_no_live_out(
4478
; CHECK-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]]) {
4579
; CHECK-NEXT: [[ENTRY:.*]]:
80+
; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
81+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 23, [[TMP0]]
82+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
83+
; CHECK: [[VECTOR_PH]]:
84+
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
85+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 23, [[TMP1]]
86+
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 23, [[N_MOD_VF]]
87+
; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
88+
; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vscale.i32()
89+
; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP3]], 1
90+
; CHECK-NEXT: [[VECTOR_RECUR_INIT:%.*]] = insertelement <vscale x 1 x i64> poison, i64 0, i32 [[TMP4]]
91+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
92+
; CHECK: [[VECTOR_BODY]]:
93+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
94+
; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <vscale x 1 x i64> [ [[VECTOR_RECUR_INIT]], %[[VECTOR_PH]] ], [ [[WIDE_LOAD:%.*]], %[[VECTOR_BODY]] ]
95+
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[INDEX]]
96+
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP5]], i32 0
97+
; CHECK-NEXT: [[WIDE_LOAD]] = load <vscale x 1 x i64>, ptr [[TMP6]], align 8
98+
; CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 1 x i64> @llvm.vector.splice.nxv1i64(<vscale x 1 x i64> [[VECTOR_RECUR]], <vscale x 1 x i64> [[WIDE_LOAD]], i32 -1)
99+
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[INDEX]]
100+
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[TMP8]], i32 0
101+
; CHECK-NEXT: store <vscale x 1 x i64> [[TMP7]], ptr [[TMP9]], align 8
102+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP2]]
103+
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
104+
; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
105+
; CHECK: [[MIDDLE_BLOCK]]:
106+
; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.vscale.i32()
107+
; CHECK-NEXT: [[TMP12:%.*]] = sub i32 [[TMP11]], 1
108+
; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <vscale x 1 x i64> [[WIDE_LOAD]], i32 [[TMP12]]
109+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 23, [[N_VEC]]
110+
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
111+
; CHECK: [[SCALAR_PH]]:
112+
; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
113+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
46114
; CHECK-NEXT: br label %[[LOOP:.*]]
47115
; CHECK: [[LOOP]]:
48-
; CHECK-NEXT: [[FOR:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[L:%.*]], %[[LOOP]] ]
49-
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
116+
; CHECK-NEXT: [[FOR:%.*]] = phi i64 [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[L:%.*]], %[[LOOP]] ]
117+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
50118
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
51119
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[IV]]
52120
; CHECK-NEXT: [[L]] = load i64, ptr [[GEP]], align 8
53121
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[IV]]
54122
; CHECK-NEXT: store i64 [[FOR]], ptr [[GEP_DST]], align 8
55123
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 22
56-
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]
124+
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
57125
; CHECK: [[EXIT]]:
58126
; CHECK-NEXT: ret void
59127
;
@@ -74,3 +142,11 @@ loop:
74142
exit:
75143
ret void
76144
}
145+
;.
146+
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
147+
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
148+
; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
149+
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
150+
; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
151+
; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
152+
;.

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