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[AMDGPU][True16][MC] test update for v_subrev_f16 in true16 (#119315)
This is a NFC change. Update mc test for v_subrev_f16 in true16 format. MC source change was done by previous patch and automatically enabled by t16 pesudo
1 parent 5270e63 commit c3241a9

17 files changed

+570
-342
lines changed

‎llvm/lib/Target/AMDGPU/VOP2Instructions.td

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1820,8 +1820,7 @@ defm V_PK_FMAC_F16 : VOP2_Real_e32_gfx11_gfx12<0x03c>;
18201820

18211821
defm V_ADD_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x032, "v_add_f16">;
18221822
defm V_SUB_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x033, "v_sub_f16">;
1823-
defm V_SUBREV_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">;
1824-
defm V_SUBREV_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">;
1823+
defm V_SUBREV_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x034, "v_subrev_f16">;
18251824
defm V_MUL_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x035, "v_mul_f16">;
18261825
defm V_FMAC_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x036, "v_fmac_f16">;
18271826
defm V_LDEXP_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x03b, "v_ldexp_f16">;

‎llvm/test/MC/AMDGPU/gfx11_asm_vop2.s

Lines changed: 45 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -2437,50 +2437,65 @@ v_subrev_co_ci_u32 v255, vcc, 0xaf123456, v255, vcc
24372437
// W64: v_subrev_co_ci_u32_e32 v255, vcc, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf]
24382438
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
24392439

2440-
v_subrev_f16 v5, v1, v2
2441-
// GFX11: v_subrev_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x68]
2440+
v_subrev_f16 v5.l, v1.l, v2.l
2441+
// GFX11: v_subrev_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x68]
24422442

2443-
v_subrev_f16 v5, v127, v2
2444-
// GFX11: v_subrev_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x68]
2443+
v_subrev_f16 v5.l, v127.l, v2.l
2444+
// GFX11: v_subrev_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x68]
24452445

2446-
v_subrev_f16 v5, s1, v2
2447-
// GFX11: v_subrev_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x68]
2446+
v_subrev_f16 v5.l, s1, v2.l
2447+
// GFX11: v_subrev_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x68]
24482448

2449-
v_subrev_f16 v5, s105, v2
2450-
// GFX11: v_subrev_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x68]
2449+
v_subrev_f16 v5.l, s105, v2.l
2450+
// GFX11: v_subrev_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x68]
24512451

2452-
v_subrev_f16 v5, vcc_lo, v2
2453-
// GFX11: v_subrev_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x68]
2452+
v_subrev_f16 v5.l, vcc_lo, v2.l
2453+
// GFX11: v_subrev_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x68]
24542454

2455-
v_subrev_f16 v5, vcc_hi, v2
2456-
// GFX11: v_subrev_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x68]
2455+
v_subrev_f16 v5.l, vcc_hi, v2.l
2456+
// GFX11: v_subrev_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x68]
24572457

2458-
v_subrev_f16 v5, ttmp15, v2
2459-
// GFX11: v_subrev_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x68]
2458+
v_subrev_f16 v5.l, ttmp15, v2.l
2459+
// GFX11: v_subrev_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x68]
24602460

2461-
v_subrev_f16 v5, m0, v2
2462-
// GFX11: v_subrev_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x68]
2461+
v_subrev_f16 v5.l, m0, v2.l
2462+
// GFX11: v_subrev_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x68]
24632463

2464-
v_subrev_f16 v5, exec_lo, v2
2465-
// GFX11: v_subrev_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x68]
2464+
v_subrev_f16 v5.l, exec_lo, v2.l
2465+
// GFX11: v_subrev_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x68]
24662466

2467-
v_subrev_f16 v5, exec_hi, v2
2468-
// GFX11: v_subrev_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x68]
2467+
v_subrev_f16 v5.l, exec_hi, v2.l
2468+
// GFX11: v_subrev_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x68]
24692469

2470-
v_subrev_f16 v5, null, v2
2471-
// GFX11: v_subrev_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x68]
2470+
v_subrev_f16 v5.l, null, v2.l
2471+
// GFX11: v_subrev_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x68]
24722472

2473-
v_subrev_f16 v5, -1, v2
2474-
// GFX11: v_subrev_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x68]
2473+
v_subrev_f16 v5.l, -1, v2.l
2474+
// GFX11: v_subrev_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x68]
24752475

2476-
v_subrev_f16 v5, 0.5, v2
2477-
// GFX11: v_subrev_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x68]
2476+
v_subrev_f16 v5.l, 0.5, v2.l
2477+
// GFX11: v_subrev_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x68]
24782478

2479-
v_subrev_f16 v5, src_scc, v2
2480-
// GFX11: v_subrev_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x68]
2479+
v_subrev_f16 v5.l, src_scc, v2.l
2480+
// GFX11: v_subrev_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x68]
24812481

2482-
v_subrev_f16 v127, 0xfe0b, v127
2483-
// GFX11: v_subrev_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00]
2482+
v_subrev_f16 v127.l, 0xfe0b, v127.l
2483+
// GFX11: v_subrev_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00]
2484+
2485+
v_subrev_f16 v5.l, v1.h, v2.l
2486+
// GFX11: v_subrev_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x68]
2487+
2488+
v_subrev_f16 v5.l, v127.h, v2.l
2489+
// GFX11: v_subrev_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x68]
2490+
2491+
v_subrev_f16 v127.l, 0.5, v127.l
2492+
// GFX11: v_subrev_f16_e32 v127.l, 0.5, v127.l ; encoding: [0xf0,0xfe,0xfe,0x68]
2493+
2494+
v_subrev_f16 v5.h, src_scc, v2.h
2495+
// GFX11: v_subrev_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x69]
2496+
2497+
v_subrev_f16 v127.h, 0xfe0b, v127.h
2498+
// GFX11: v_subrev_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x69,0x0b,0xfe,0x00,0x00]
24842499

24852500
v_subrev_f32 v5, v1, v2
24862501
// GFX11: v_subrev_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x0a]

‎llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s

Lines changed: 37 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1958,47 +1958,56 @@ v_subrev_co_ci_u32 v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mas
19581958
// W64: v_subrev_co_ci_u32_dpp v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x45,0xff,0x6f,0x05,0x30]
19591959
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
19601960

1961-
v_subrev_f16 v5, v1, v2 quad_perm:[3,2,1,0]
1962-
// GFX11: v_subrev_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff]
1961+
v_subrev_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
1962+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff]
19631963

1964-
v_subrev_f16 v5, v1, v2 quad_perm:[0,1,2,3]
1965-
// GFX11: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff]
1964+
v_subrev_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
1965+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff]
19661966

1967-
v_subrev_f16 v5, v1, v2 row_mirror
1968-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff]
1967+
v_subrev_f16 v5.l, v1.l, v2.l row_mirror
1968+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff]
19691969

1970-
v_subrev_f16 v5, v1, v2 row_half_mirror
1971-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff]
1970+
v_subrev_f16 v5.l, v1.l, v2.l row_half_mirror
1971+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff]
19721972

1973-
v_subrev_f16 v5, v1, v2 row_shl:1
1974-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff]
1973+
v_subrev_f16 v5.l, v1.l, v2.l row_shl:1
1974+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff]
19751975

1976-
v_subrev_f16 v5, v1, v2 row_shl:15
1977-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff]
1976+
v_subrev_f16 v5.l, v1.l, v2.l row_shl:15
1977+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff]
19781978

1979-
v_subrev_f16 v5, v1, v2 row_shr:1
1980-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff]
1979+
v_subrev_f16 v5.l, v1.l, v2.l row_shr:1
1980+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff]
19811981

1982-
v_subrev_f16 v5, v1, v2 row_shr:15
1983-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff]
1982+
v_subrev_f16 v5.l, v1.l, v2.l row_shr:15
1983+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff]
19841984

1985-
v_subrev_f16 v5, v1, v2 row_ror:1
1986-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff]
1985+
v_subrev_f16 v5.l, v1.l, v2.l row_ror:1
1986+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff]
19871987

1988-
v_subrev_f16 v5, v1, v2 row_ror:15
1989-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff]
1988+
v_subrev_f16 v5.l, v1.l, v2.l row_ror:15
1989+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff]
19901990

1991-
v_subrev_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
1992-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff]
1991+
v_subrev_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
1992+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff]
19931993

1994-
v_subrev_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
1995-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01]
1994+
v_subrev_f16 v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
1995+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01]
19961996

1997-
v_subrev_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1998-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x09,0x13]
1997+
v_subrev_f16 v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
1998+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x09,0x13]
19991999

2000-
v_subrev_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
2001-
// GFX11: v_subrev_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xf5,0x30]
2000+
v_subrev_f16 v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
2001+
// GFX11: v_subrev_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xf5,0x30]
2002+
2003+
v_subrev_f16 v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
2004+
// GFX11: v_subrev_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x5f,0x01,0x01]
2005+
2006+
v_subrev_f16 v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
2007+
// GFX11: v_subrev_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0b,0x69,0x81,0x60,0x09,0x13]
2008+
2009+
v_subrev_f16 v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
2010+
// GFX11: v_subrev_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x69,0xff,0x6f,0xf5,0x30]
20022011

20032012
v_subrev_f32 v5, v1, v2 quad_perm:[3,2,1,0]
20042013
// GFX11: v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0xff]

‎llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s

Lines changed: 15 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -463,14 +463,23 @@ v_subrev_co_ci_u32 v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:0
463463
// W64: v_subrev_co_ci_u32_dpp v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xff,0x45,0xff,0x00,0x00,0x00]
464464
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
465465

466-
v_subrev_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
467-
// GFX11: v_subrev_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
466+
v_subrev_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
467+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
468468

469-
v_subrev_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
470-
// GFX11: v_subrev_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
469+
v_subrev_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
470+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
471471

472-
v_subrev_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
473-
// GFX11: v_subrev_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00]
472+
v_subrev_f16 v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0]
473+
// GFX11: v_subrev_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00]
474+
475+
v_subrev_f16 v127.l, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0]
476+
// GFX11: v_subrev_f16_dpp v127.l, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfe,0x68,0x7f,0x77,0x39,0x05]
477+
478+
v_subrev_f16 v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
479+
// GFX11: v_subrev_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0b,0x69,0x81,0x77,0x39,0x05]
480+
481+
v_subrev_f16 v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
482+
// GFX11: v_subrev_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xff,0x69,0xff,0x00,0x00,0x00]
474483

475484
v_subrev_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
476485
// GFX11: v_subrev_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x0a,0x01,0x77,0x39,0x05]

‎llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s

Lines changed: 44 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -416,30 +416,56 @@ v_sub_f16_e32 v5.l, v1.l, v255.l
416416
v_sub_f16_e32 v5.l, v255.l, v2.l
417417
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
418418

419-
v_subrev_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
420-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
419+
v_subrev_f16_dpp v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
420+
// GFX11: :[[@LINE-1]]:18: error: invalid operand for instruction
421421

422-
v_subrev_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0]
423-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
422+
v_subrev_f16_dpp v255.h, v1.h, v2.h quad_perm:[3,2,1,0]
423+
// GFX11: :[[@LINE-1]]:18: error: invalid operand for instruction
424424

425-
v_subrev_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
426-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
425+
v_subrev_f16_dpp v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
426+
// GFX11: :[[@LINE-1]]:18: error: invalid operand for instruction
427427

428+
v_subrev_f16_dpp v255.l, v1.l, v2.l quad_perm:[3,2,1,0]
429+
// GFX11: :[[@LINE-1]]:18: error: invalid operand for instruction
428430

429-
v_subrev_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0]
430-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
431+
v_subrev_f16_dpp v5.h, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
432+
// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
431433

432-
v_subrev_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
433-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
434+
v_subrev_f16_dpp v5.h, v1.h, v255.h quad_perm:[3,2,1,0]
435+
// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
434436

435-
v_subrev_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0]
436-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
437+
v_subrev_f16_dpp v5.h, v255.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
438+
// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
437439

438-
v_subrev_f16_e32 v255, v1, v2
439-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
440+
v_subrev_f16_dpp v5.h, v255.h, v2.h quad_perm:[3,2,1,0]
441+
// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
440442

441-
v_subrev_f16_e32 v5, v1, v255
442-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
443+
v_subrev_f16_dpp v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
444+
// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
443445

444-
v_subrev_f16_e32 v5, v255, v2
445-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
446+
v_subrev_f16_dpp v5.l, v1.l, v255.l quad_perm:[3,2,1,0]
447+
// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
448+
449+
v_subrev_f16_dpp v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
450+
// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
451+
452+
v_subrev_f16_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0]
453+
// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
454+
455+
v_subrev_f16_e32 v255.h, v1.h, v2.h
456+
// GFX11: :[[@LINE-1]]:18: error: invalid operand for instruction
457+
458+
v_subrev_f16_e32 v255.l, v1.l, v2.l
459+
// GFX11: :[[@LINE-1]]:18: error: invalid operand for instruction
460+
461+
v_subrev_f16_e32 v5.h, v1.h, v255.h
462+
// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
463+
464+
v_subrev_f16_e32 v5.h, v255.h, v2.h
465+
// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
466+
467+
v_subrev_f16_e32 v5.l, v1.l, v255.l
468+
// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
469+
470+
v_subrev_f16_e32 v5.l, v255.l, v2.l
471+
// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction

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