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Fix tests after rebase
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‎llvm/test/CodeGen/AArch64/sme2p1-intrinsics-movaz.ll

Lines changed: 34 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
; X2 - Horiz
99
;;
1010

11-
define {<vscale x 16 x i8>, <vscale x 16 x i8>} @test_readz_hor_z8_i8_x2(i32 %tile, i32 %slice) {
11+
define {<vscale x 16 x i8>, <vscale x 16 x i8>} @test_readz_hor_z8_i8_x2(i32 %tile, i32 %slice) #0 {
1212
; CHECK-LABEL: test_readz_hor_z8_i8_x2:
1313
; CHECK: // %bb.0:
1414
; CHECK-NEXT: mov w12, w1
@@ -20,7 +20,7 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>} @test_readz_hor_z8_i8_x2(i32 %ti
2020
%res2 = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %slice.max)
2121
ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %res2
2222
}
23-
define {<vscale x 8 x i16>, <vscale x 8 x i16>} @test_readz_hor_z16_i16_x2(i32 %slice) {
23+
define {<vscale x 8 x i16>, <vscale x 8 x i16>} @test_readz_hor_z16_i16_x2(i32 %slice) #0 {
2424
; CHECK-LABEL: test_readz_hor_z16_i16_x2:
2525
; CHECK: // %bb.0:
2626
; CHECK-NEXT: mov w12, w0
@@ -33,7 +33,7 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>} @test_readz_hor_z16_i16_x2(i32 %
3333
ret {<vscale x 8 x i16>, <vscale x 8 x i16>} %res2
3434
}
3535

36-
define {<vscale x 4 x i32>, <vscale x 4 x i32>} @test_readz_hor_z32_i32_x2(i32 %slice) {
36+
define {<vscale x 4 x i32>, <vscale x 4 x i32>} @test_readz_hor_z32_i32_x2(i32 %slice) #0 {
3737
; CHECK-LABEL: test_readz_hor_z32_i32_x2:
3838
; CHECK: // %bb.0:
3939
; CHECK-NEXT: mov w12, w0
@@ -46,7 +46,7 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>} @test_readz_hor_z32_i32_x2(i32 %
4646
ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %res2
4747
}
4848

49-
define {<vscale x 2 x i64>, <vscale x 2 x i64>} @test_readz_hor_z64_i64_x2(i32 %slice) {
49+
define {<vscale x 2 x i64>, <vscale x 2 x i64>} @test_readz_hor_z64_i64_x2(i32 %slice) #0 {
5050
; CHECK-LABEL: test_readz_hor_z64_i64_x2:
5151
; CHECK: // %bb.0:
5252
; CHECK-NEXT: mov w12, w0
@@ -58,7 +58,7 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>} @test_readz_hor_z64_i64_x2(i32 %
5858
ret {<vscale x 2 x i64>, <vscale x 2 x i64>} %res
5959
}
6060

61-
define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @test_readz_hor_z16_bf16_x2(i32 %slice) {
61+
define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @test_readz_hor_z16_bf16_x2(i32 %slice) #0 {
6262
; CHECK-LABEL: test_readz_hor_z16_bf16_x2:
6363
; CHECK: // %bb.0:
6464
; CHECK-NEXT: mov w12, w0
@@ -71,7 +71,7 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @test_readz_hor_z16_bf16_x
7171
ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %res2
7272
}
7373

74-
define {<vscale x 8 x half>, <vscale x 8 x half>} @test_readz_hor_z16_f16_x2(i32 %slice) {
74+
define {<vscale x 8 x half>, <vscale x 8 x half>} @test_readz_hor_z16_f16_x2(i32 %slice) #0 {
7575
; CHECK-LABEL: test_readz_hor_z16_f16_x2:
7676
; CHECK: // %bb.0:
7777
; CHECK-NEXT: mov w12, w0
@@ -84,7 +84,7 @@ define {<vscale x 8 x half>, <vscale x 8 x half>} @test_readz_hor_z16_f16_x2(i32
8484
ret {<vscale x 8 x half>, <vscale x 8 x half>} %res2
8585
}
8686

87-
define {<vscale x 4 x float>, <vscale x 4 x float>} @test_readz_hor_z32_f32_x2(i32 %slice) {
87+
define {<vscale x 4 x float>, <vscale x 4 x float>} @test_readz_hor_z32_f32_x2(i32 %slice) #0 {
8888
; CHECK-LABEL: test_readz_hor_z32_f32_x2:
8989
; CHECK: // %bb.0:
9090
; CHECK-NEXT: mov w12, w0
@@ -97,7 +97,7 @@ define {<vscale x 4 x float>, <vscale x 4 x float>} @test_readz_hor_z32_f32_x2(i
9797
ret {<vscale x 4 x float>, <vscale x 4 x float>} %res2
9898
}
9999

100-
define {<vscale x 2 x double>, <vscale x 2 x double>} @test_readz_hor_z64_f64_x2(i32 %slice) {
100+
define {<vscale x 2 x double>, <vscale x 2 x double>} @test_readz_hor_z64_f64_x2(i32 %slice) #0 {
101101
; CHECK-LABEL: test_readz_hor_z64_f64_x2:
102102
; CHECK: // %bb.0:
103103
; CHECK-NEXT: mov w12, w0
@@ -113,7 +113,7 @@ define {<vscale x 2 x double>, <vscale x 2 x double>} @test_readz_hor_z64_f64_x2
113113
; X2- Vert
114114
;;
115115

116-
define {<vscale x 16 x i8>, <vscale x 16 x i8>} @test_readz_ver_z8_i8_x2(i32 %tile, i32 %slice) {
116+
define {<vscale x 16 x i8>, <vscale x 16 x i8>} @test_readz_ver_z8_i8_x2(i32 %tile, i32 %slice) #0 {
117117
; CHECK-LABEL: test_readz_ver_z8_i8_x2:
118118
; CHECK: // %bb.0:
119119
; CHECK-NEXT: mov w12, w1
@@ -125,7 +125,7 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>} @test_readz_ver_z8_i8_x2(i32 %ti
125125
%res2 = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %slice.max)
126126
ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %res2
127127
}
128-
define {<vscale x 8 x i16>, <vscale x 8 x i16>} @test_readz_ver_z16_i16_x2(i32 %slice) {
128+
define {<vscale x 8 x i16>, <vscale x 8 x i16>} @test_readz_ver_z16_i16_x2(i32 %slice) #0 {
129129
; CHECK-LABEL: test_readz_ver_z16_i16_x2:
130130
; CHECK: // %bb.0:
131131
; CHECK-NEXT: mov w12, w0
@@ -138,7 +138,7 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>} @test_readz_ver_z16_i16_x2(i32 %
138138
ret {<vscale x 8 x i16>, <vscale x 8 x i16>} %res2
139139
}
140140

141-
define {<vscale x 4 x i32>, <vscale x 4 x i32>} @test_readz_ver_z32_i32_x2(i32 %slice) {
141+
define {<vscale x 4 x i32>, <vscale x 4 x i32>} @test_readz_ver_z32_i32_x2(i32 %slice) #0 {
142142
; CHECK-LABEL: test_readz_ver_z32_i32_x2:
143143
; CHECK: // %bb.0:
144144
; CHECK-NEXT: mov w12, w0
@@ -151,7 +151,7 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>} @test_readz_ver_z32_i32_x2(i32 %
151151
ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %res2
152152
}
153153

154-
define {<vscale x 2 x i64>, <vscale x 2 x i64>} @test_readz_ver_z64_i64_x2(i32 %slice) {
154+
define {<vscale x 2 x i64>, <vscale x 2 x i64>} @test_readz_ver_z64_i64_x2(i32 %slice) #0 {
155155
; CHECK-LABEL: test_readz_ver_z64_i64_x2:
156156
; CHECK: // %bb.0:
157157
; CHECK-NEXT: mov w12, w0
@@ -163,7 +163,7 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>} @test_readz_ver_z64_i64_x2(i32 %
163163
ret {<vscale x 2 x i64>, <vscale x 2 x i64>} %res
164164
}
165165

166-
define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @test_readz_ver_z16_bf16_x2(i32 %slice) {
166+
define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @test_readz_ver_z16_bf16_x2(i32 %slice) #0 {
167167
; CHECK-LABEL: test_readz_ver_z16_bf16_x2:
168168
; CHECK: // %bb.0:
169169
; CHECK-NEXT: mov w12, w0
@@ -176,7 +176,7 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @test_readz_ver_z16_bf16_x
176176
ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %res2
177177
}
178178

179-
define {<vscale x 8 x half>, <vscale x 8 x half>} @test_readz_ver_z16_f16_x2(i32 %slice) {
179+
define {<vscale x 8 x half>, <vscale x 8 x half>} @test_readz_ver_z16_f16_x2(i32 %slice) #0 {
180180
; CHECK-LABEL: test_readz_ver_z16_f16_x2:
181181
; CHECK: // %bb.0:
182182
; CHECK-NEXT: mov w12, w0
@@ -189,7 +189,7 @@ define {<vscale x 8 x half>, <vscale x 8 x half>} @test_readz_ver_z16_f16_x2(i32
189189
ret {<vscale x 8 x half>, <vscale x 8 x half>} %res2
190190
}
191191

192-
define {<vscale x 4 x float>, <vscale x 4 x float>} @test_readz_ver_z32_f32_x2(i32 %slice) {
192+
define {<vscale x 4 x float>, <vscale x 4 x float>} @test_readz_ver_z32_f32_x2(i32 %slice) #0 {
193193
; CHECK-LABEL: test_readz_ver_z32_f32_x2:
194194
; CHECK: // %bb.0:
195195
; CHECK-NEXT: mov w12, w0
@@ -202,7 +202,7 @@ define {<vscale x 4 x float>, <vscale x 4 x float>} @test_readz_ver_z32_f32_x2(i
202202
ret {<vscale x 4 x float>, <vscale x 4 x float>} %res2
203203
}
204204

205-
define {<vscale x 2 x double>, <vscale x 2 x double>} @test_readz_ver_z64_f64_x2(i32 %slice) {
205+
define {<vscale x 2 x double>, <vscale x 2 x double>} @test_readz_ver_z64_f64_x2(i32 %slice) #0 {
206206
; CHECK-LABEL: test_readz_ver_z64_f64_x2:
207207
; CHECK: // %bb.0:
208208
; CHECK-NEXT: mov w12, w0
@@ -218,7 +218,7 @@ define {<vscale x 2 x double>, <vscale x 2 x double>} @test_readz_ver_z64_f64_x2
218218
; X4 - Horiz
219219
;;
220220

221-
define {<vscale x 16 x i8>, <vscale x 16 x i8>,<vscale x 16 x i8>, <vscale x 16 x i8>} @test_readz_hor_z8_i8_x4(i32 %tile, i32 %slice) {
221+
define {<vscale x 16 x i8>, <vscale x 16 x i8>,<vscale x 16 x i8>, <vscale x 16 x i8>} @test_readz_hor_z8_i8_x4(i32 %tile, i32 %slice) #0 {
222222
; CHECK-LABEL: test_readz_hor_z8_i8_x4:
223223
; CHECK: // %bb.0:
224224
; CHECK-NEXT: mov w12, w1
@@ -230,7 +230,7 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>,<vscale x 16 x i8>, <vscale x 16
230230
%res2 = call {<vscale x 16 x i8>, <vscale x 16 x i8>,<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.aarch64.sme.readz.horiz.x4.nxv16i8(i32 0, i32 %slice.max)
231231
ret {<vscale x 16 x i8>, <vscale x 16 x i8>,<vscale x 16 x i8>, <vscale x 16 x i8>} %res2
232232
}
233-
define {<vscale x 8 x i16>, <vscale x 8 x i16>,<vscale x 8 x i16>, <vscale x 8 x i16>} @test_readz_hor_z16_i16_x4(i32 %slice) {
233+
define {<vscale x 8 x i16>, <vscale x 8 x i16>,<vscale x 8 x i16>, <vscale x 8 x i16>} @test_readz_hor_z16_i16_x4(i32 %slice) #0 {
234234
; CHECK-LABEL: test_readz_hor_z16_i16_x4:
235235
; CHECK: // %bb.0:
236236
; CHECK-NEXT: mov w12, w0
@@ -243,7 +243,7 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>,<vscale x 8 x i16>, <vscale x 8 x
243243
ret {<vscale x 8 x i16>, <vscale x 8 x i16>,<vscale x 8 x i16>, <vscale x 8 x i16>} %res2
244244
}
245245

246-
define {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} @test_readz_hor_z32_i32_x4(i32 %slice) {
246+
define {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} @test_readz_hor_z32_i32_x4(i32 %slice) #0 {
247247
; CHECK-LABEL: test_readz_hor_z32_i32_x4:
248248
; CHECK: // %bb.0:
249249
; CHECK-NEXT: mov w12, w0
@@ -255,7 +255,7 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x
255255
ret {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} %res2
256256
}
257257

258-
define {<vscale x 2 x i64>, <vscale x 2 x i64>,<vscale x 2 x i64>, <vscale x 2 x i64>} @test_readz_hor_z64_i64_x4(i32 %slice) {
258+
define {<vscale x 2 x i64>, <vscale x 2 x i64>,<vscale x 2 x i64>, <vscale x 2 x i64>} @test_readz_hor_z64_i64_x4(i32 %slice) #0 {
259259
; CHECK-LABEL: test_readz_hor_z64_i64_x4:
260260
; CHECK: // %bb.0:
261261
; CHECK-NEXT: mov w12, w0
@@ -267,7 +267,7 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>,<vscale x 2 x i64>, <vscale x 2 x
267267
ret {<vscale x 2 x i64>, <vscale x 2 x i64>,<vscale x 2 x i64>, <vscale x 2 x i64>} %res
268268
}
269269

270-
define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @test_readz_hor_z16_bf16_x4(i32 %slice) {
270+
define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @test_readz_hor_z16_bf16_x4(i32 %slice) #0 {
271271
; CHECK-LABEL: test_readz_hor_z16_bf16_x4:
272272
; CHECK: // %bb.0:
273273
; CHECK-NEXT: mov w12, w0
@@ -280,7 +280,7 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vs
280280
ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %res2
281281
}
282282

283-
define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} @test_readz_hor_z16_f16_x4(i32 %slice) {
283+
define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} @test_readz_hor_z16_f16_x4(i32 %slice) #0 {
284284
; CHECK-LABEL: test_readz_hor_z16_f16_x4:
285285
; CHECK: // %bb.0:
286286
; CHECK-NEXT: mov w12, w0
@@ -293,7 +293,7 @@ define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
293293
ret {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} %res2
294294
}
295295

296-
define {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} @test_readz_hor_z32_f32_x4(i32 %slice) {
296+
define {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} @test_readz_hor_z32_f32_x4(i32 %slice) #0 {
297297
; CHECK-LABEL: test_readz_hor_z32_f32_x4:
298298
; CHECK: // %bb.0:
299299
; CHECK-NEXT: mov w12, w0
@@ -305,7 +305,7 @@ define {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale
305305
ret {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} %res2
306306
}
307307

308-
define {<vscale x 2 x double>, <vscale x 2 x double>,<vscale x 2 x double>, <vscale x 2 x double>} @test_readz_hor_z64_f64_x4(i32 %slice) {
308+
define {<vscale x 2 x double>, <vscale x 2 x double>,<vscale x 2 x double>, <vscale x 2 x double>} @test_readz_hor_z64_f64_x4(i32 %slice) #0 {
309309
; CHECK-LABEL: test_readz_hor_z64_f64_x4:
310310
; CHECK: // %bb.0:
311311
; CHECK-NEXT: mov w12, w0
@@ -321,7 +321,7 @@ define {<vscale x 2 x double>, <vscale x 2 x double>,<vscale x 2 x double>, <vsc
321321
; X4 - Vert
322322
;;
323323

324-
define {<vscale x 16 x i8>, <vscale x 16 x i8>,<vscale x 16 x i8>, <vscale x 16 x i8>} @test_readz_ver_z8_i8_x4(i32 %tile, i32 %slice) {
324+
define {<vscale x 16 x i8>, <vscale x 16 x i8>,<vscale x 16 x i8>, <vscale x 16 x i8>} @test_readz_ver_z8_i8_x4(i32 %tile, i32 %slice) #0 {
325325
; CHECK-LABEL: test_readz_ver_z8_i8_x4:
326326
; CHECK: // %bb.0:
327327
; CHECK-NEXT: mov w12, w1
@@ -333,7 +333,7 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>,<vscale x 16 x i8>, <vscale x 16
333333
%res2 = call {<vscale x 16 x i8>, <vscale x 16 x i8>,<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.aarch64.sme.readz.vert.x4.nxv16i8(i32 0, i32 %slice.max)
334334
ret {<vscale x 16 x i8>, <vscale x 16 x i8>,<vscale x 16 x i8>, <vscale x 16 x i8>} %res2
335335
}
336-
define {<vscale x 8 x i16>, <vscale x 8 x i16>,<vscale x 8 x i16>, <vscale x 8 x i16>} @test_readz_ver_z16_i16_x4(i32 %slice) {
336+
define {<vscale x 8 x i16>, <vscale x 8 x i16>,<vscale x 8 x i16>, <vscale x 8 x i16>} @test_readz_ver_z16_i16_x4(i32 %slice) #0 {
337337
; CHECK-LABEL: test_readz_ver_z16_i16_x4:
338338
; CHECK: // %bb.0:
339339
; CHECK-NEXT: mov w12, w0
@@ -346,7 +346,7 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>,<vscale x 8 x i16>, <vscale x 8 x
346346
ret {<vscale x 8 x i16>, <vscale x 8 x i16>,<vscale x 8 x i16>, <vscale x 8 x i16>} %res2
347347
}
348348

349-
define {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} @test_readz_ver_z32_i32_x4(i32 %slice) {
349+
define {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} @test_readz_ver_z32_i32_x4(i32 %slice) #0 {
350350
; CHECK-LABEL: test_readz_ver_z32_i32_x4:
351351
; CHECK: // %bb.0:
352352
; CHECK-NEXT: mov w12, w0
@@ -358,7 +358,7 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x
358358
ret {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} %res2
359359
}
360360

361-
define {<vscale x 2 x i64>, <vscale x 2 x i64>,<vscale x 2 x i64>, <vscale x 2 x i64>} @test_readz_ver_z64_i64_x4(i32 %slice) {
361+
define {<vscale x 2 x i64>, <vscale x 2 x i64>,<vscale x 2 x i64>, <vscale x 2 x i64>} @test_readz_ver_z64_i64_x4(i32 %slice) #0 {
362362
; CHECK-LABEL: test_readz_ver_z64_i64_x4:
363363
; CHECK: // %bb.0:
364364
; CHECK-NEXT: mov w12, w0
@@ -370,7 +370,7 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>,<vscale x 2 x i64>, <vscale x 2 x
370370
ret {<vscale x 2 x i64>, <vscale x 2 x i64>,<vscale x 2 x i64>, <vscale x 2 x i64>} %res
371371
}
372372

373-
define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @test_readz_ver_z16_bf16_x4(i32 %slice) {
373+
define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @test_readz_ver_z16_bf16_x4(i32 %slice) #0 {
374374
; CHECK-LABEL: test_readz_ver_z16_bf16_x4:
375375
; CHECK: // %bb.0:
376376
; CHECK-NEXT: mov w12, w0
@@ -383,7 +383,7 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vs
383383
ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %res2
384384
}
385385

386-
define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} @test_readz_ver_z16_f16_x4(i32 %slice) {
386+
define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} @test_readz_ver_z16_f16_x4(i32 %slice) #0 {
387387
; CHECK-LABEL: test_readz_ver_z16_f16_x4:
388388
; CHECK: // %bb.0:
389389
; CHECK-NEXT: mov w12, w0
@@ -396,7 +396,7 @@ define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
396396
ret {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} %res2
397397
}
398398

399-
define {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} @test_readz_ver_z32_f32_x4(i32 %slice) {
399+
define {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} @test_readz_ver_z32_f32_x4(i32 %slice) #0 {
400400
; CHECK-LABEL: test_readz_ver_z32_f32_x4:
401401
; CHECK: // %bb.0:
402402
; CHECK-NEXT: mov w12, w0
@@ -408,7 +408,7 @@ define {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale
408408
ret {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} %res2
409409
}
410410

411-
define {<vscale x 2 x double>, <vscale x 2 x double>,<vscale x 2 x double>, <vscale x 2 x double>} @test_readz_ver_z64_f64_x4(i32 %slice) {
411+
define {<vscale x 2 x double>, <vscale x 2 x double>,<vscale x 2 x double>, <vscale x 2 x double>} @test_readz_ver_z64_f64_x4(i32 %slice) #0 {
412412
; CHECK-LABEL: test_readz_ver_z64_f64_x4:
413413
; CHECK: // %bb.0:
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; CHECK-NEXT: mov w12, w0
@@ -420,6 +420,8 @@ define {<vscale x 2 x double>, <vscale x 2 x double>,<vscale x 2 x double>, <vsc
420420
ret {<vscale x 2 x double>, <vscale x 2 x double>,<vscale x 2 x double>, <vscale x 2 x double>} %res
421421
}
422422

423+
attributes #0 = { "target-features"="+sve" }
424+
423425
declare {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.aarch64.sme.readz.horiz.za8.x2.nxv16i8(i32, i32)
424426
declare {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32, i32)
425427
declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32, i32)

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