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[AMDGPU] Move AMDGPUCodeGenPassBuilder into AMDGPUTargetMachine (NFC)
This will allow us to reuse the existing flags and the static functions while building the pipeline for new pass manager.
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7 files changed

+112
-143
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7 files changed

+112
-143
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp

Lines changed: 0 additions & 97 deletions
This file was deleted.

‎llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.h

Lines changed: 0 additions & 33 deletions
This file was deleted.

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Lines changed: 90 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -7,15 +7,16 @@
77
//===----------------------------------------------------------------------===//
88
//
99
/// \file
10-
/// The AMDGPU target machine contains all of the hardware specific
11-
/// information needed to emit code for SI+ GPUs.
10+
/// This file contains both AMDGPU target machine and the CodeGen pass builder.
11+
/// The AMDGPU target machine contains all of the hardware specific information
12+
/// needed to emit code for SI+ GPUs in the legacy pass manager pipeline. The
13+
/// CodeGen pass builder handles the pass pipeline for new pass manager.
1214
//
1315
//===----------------------------------------------------------------------===//
1416

1517
#include "AMDGPUTargetMachine.h"
1618
#include "AMDGPU.h"
1719
#include "AMDGPUAliasAnalysis.h"
18-
#include "AMDGPUCodeGenPassBuilder.h"
1920
#include "AMDGPUCtorDtorLowering.h"
2021
#include "AMDGPUExportClustering.h"
2122
#include "AMDGPUIGroupLP.h"
@@ -40,6 +41,7 @@
4041
#include "Utils/AMDGPUBaseInfo.h"
4142
#include "llvm/Analysis/CGSCCPassManager.h"
4243
#include "llvm/Analysis/CallGraphSCCPass.h"
44+
#include "llvm/Analysis/UniformityAnalysis.h"
4345
#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
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#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
@@ -64,10 +66,16 @@
6466
#include "llvm/Transforms/IPO/GlobalDCE.h"
6567
#include "llvm/Transforms/IPO/Internalize.h"
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#include "llvm/Transforms/Scalar.h"
69+
#include "llvm/Transforms/Scalar/FlattenCFG.h"
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#include "llvm/Transforms/Scalar/GVN.h"
6871
#include "llvm/Transforms/Scalar/InferAddressSpaces.h"
72+
#include "llvm/Transforms/Scalar/Sink.h"
73+
#include "llvm/Transforms/Scalar/StructurizeCFG.h"
6974
#include "llvm/Transforms/Utils.h"
75+
#include "llvm/Transforms/Utils/FixIrreducible.h"
76+
#include "llvm/Transforms/Utils/LCSSA.h"
7077
#include "llvm/Transforms/Utils/SimplifyLibCalls.h"
78+
#include "llvm/Transforms/Utils/UnifyLoopExits.h"
7179
#include "llvm/Transforms/Vectorize/LoadStoreVectorizer.h"
7280
#include <optional>
7381

@@ -930,7 +938,7 @@ Error GCNTargetMachine::buildCodeGenPipeline(
930938
}
931939

932940
//===----------------------------------------------------------------------===//
933-
// AMDGPU Pass Setup
941+
// AMDGPU Legacy Pass Setup
934942
//===----------------------------------------------------------------------===//
935943

936944
std::unique_ptr<CSEConfigBase> llvm::AMDGPUPassConfig::getCSEConfig() const {
@@ -1214,7 +1222,7 @@ MachineFunctionInfo *R600TargetMachine::createMachineFunctionInfo(
12141222
}
12151223

12161224
//===----------------------------------------------------------------------===//
1217-
// GCN Pass Setup
1225+
// GCN Legacy Pass Setup
12181226
//===----------------------------------------------------------------------===//
12191227

12201228
ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
@@ -1751,3 +1759,80 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
17511759

17521760
return false;
17531761
}
1762+
1763+
//===----------------------------------------------------------------------===//
1764+
// AMDGPU CodeGen Pass Builder interface.
1765+
//===----------------------------------------------------------------------===//
1766+
1767+
AMDGPUCodeGenPassBuilder::AMDGPUCodeGenPassBuilder(
1768+
GCNTargetMachine &TM, const CGPassBuilderOption &Opts,
1769+
PassInstrumentationCallbacks *PIC)
1770+
: CodeGenPassBuilder(TM, Opts, PIC) {
1771+
Opt.RequiresCodeGenSCCOrder = true;
1772+
// Exceptions and StackMaps are not supported, so these passes will never do
1773+
// anything.
1774+
// Garbage collection is not supported.
1775+
disablePass<StackMapLivenessPass, FuncletLayoutPass,
1776+
ShadowStackGCLoweringPass>();
1777+
}
1778+
1779+
void AMDGPUCodeGenPassBuilder::addPreISel(AddIRPass &addPass) const {
1780+
const bool LateCFGStructurize = AMDGPUTargetMachine::EnableLateStructurizeCFG;
1781+
const bool DisableStructurizer = AMDGPUTargetMachine::DisableStructurizer;
1782+
const bool EnableStructurizerWorkarounds =
1783+
AMDGPUTargetMachine::EnableStructurizerWorkarounds;
1784+
1785+
if (TM.getOptLevel() > CodeGenOptLevel::None)
1786+
addPass(FlattenCFGPass());
1787+
1788+
if (TM.getOptLevel() > CodeGenOptLevel::None)
1789+
addPass(SinkingPass());
1790+
1791+
addPass(AMDGPULateCodeGenPreparePass(TM));
1792+
1793+
// Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1794+
// regions formed by them.
1795+
1796+
addPass(AMDGPUUnifyDivergentExitNodesPass());
1797+
1798+
if (!LateCFGStructurize && !DisableStructurizer) {
1799+
if (EnableStructurizerWorkarounds) {
1800+
addPass(FixIrreduciblePass());
1801+
addPass(UnifyLoopExitsPass());
1802+
}
1803+
1804+
addPass(StructurizeCFGPass(/*SkipUniformRegions=*/false));
1805+
}
1806+
1807+
addPass(AMDGPUAnnotateUniformValuesPass());
1808+
1809+
if (!LateCFGStructurize && !DisableStructurizer) {
1810+
addPass(SIAnnotateControlFlowPass(TM));
1811+
1812+
// TODO: Move this right after structurizeCFG to avoid extra divergence
1813+
// analysis. This depends on stopping SIAnnotateControlFlow from making
1814+
// control flow modifications.
1815+
addPass(AMDGPURewriteUndefForPHIPass());
1816+
}
1817+
1818+
addPass(LCSSAPass());
1819+
1820+
if (TM.getOptLevel() > CodeGenOptLevel::Less)
1821+
addPass(AMDGPUPerfHintAnalysisPass(TM));
1822+
1823+
// FIXME: Why isn't this queried as required from AMDGPUISelDAGToDAG, and why
1824+
// isn't this in addInstSelector?
1825+
addPass(RequireAnalysisPass<UniformityInfoAnalysis, Function>());
1826+
}
1827+
1828+
void AMDGPUCodeGenPassBuilder::addAsmPrinter(AddMachinePass &addPass,
1829+
CreateMCStreamer) const {
1830+
// TODO: Add AsmPrinter.
1831+
}
1832+
1833+
Error AMDGPUCodeGenPassBuilder::addInstSelector(AddMachinePass &addPass) const {
1834+
addPass(AMDGPUISelDAGToDAGPass(TM));
1835+
addPass(SIFixSGPRCopiesPass());
1836+
addPass(SILowerI1CopiesPass());
1837+
return Error::success();
1838+
}

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h

Lines changed: 22 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,8 @@
1616

1717
#include "GCNSubtarget.h"
1818
#include "llvm/CodeGen/TargetPassConfig.h"
19+
#include "llvm/MC/MCStreamer.h"
20+
#include "llvm/Passes/CodeGenPassBuilder.h"
1921
#include "llvm/Target/TargetMachine.h"
2022
#include <optional>
2123
#include <utility>
@@ -47,7 +49,8 @@ class AMDGPUTargetMachine : public LLVMTargetMachine {
4749
~AMDGPUTargetMachine() override;
4850

4951
const TargetSubtargetInfo *getSubtargetImpl() const;
50-
const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override = 0;
52+
const TargetSubtargetInfo *
53+
getSubtargetImpl(const Function &) const override = 0;
5154

5255
TargetLoweringObjectFile *getObjFileLowering() const override {
5356
return TLOF.get();
@@ -94,9 +97,7 @@ class GCNTargetMachine final : public AMDGPUTargetMachine {
9497

9598
TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
9699

97-
bool useIPRA() const override {
98-
return true;
99-
}
100+
bool useIPRA() const override { return true; }
100101

101102
Error buildCodeGenPipeline(ModulePassManager &MPM, raw_pwrite_stream &Out,
102103
raw_pwrite_stream *DwoOut,
@@ -120,7 +121,7 @@ class GCNTargetMachine final : public AMDGPUTargetMachine {
120121
};
121122

122123
//===----------------------------------------------------------------------===//
123-
// AMDGPU Pass Setup
124+
// AMDGPU Pass Setup - For Legacy Pass Manager.
124125
//===----------------------------------------------------------------------===//
125126

126127
class AMDGPUPassConfig : public TargetPassConfig {
@@ -158,6 +159,22 @@ class AMDGPUPassConfig : public TargetPassConfig {
158159
}
159160
};
160161

162+
//===----------------------------------------------------------------------===//
163+
// AMDGPU CodeGen Pass Builder interface.
164+
//===----------------------------------------------------------------------===//
165+
166+
class AMDGPUCodeGenPassBuilder
167+
: public CodeGenPassBuilder<AMDGPUCodeGenPassBuilder, GCNTargetMachine> {
168+
public:
169+
AMDGPUCodeGenPassBuilder(GCNTargetMachine &TM,
170+
const CGPassBuilderOption &Opts,
171+
PassInstrumentationCallbacks *PIC);
172+
173+
void addPreISel(AddIRPass &addPass) const;
174+
void addAsmPrinter(AddMachinePass &, CreateMCStreamer) const;
175+
Error addInstSelector(AddMachinePass &) const;
176+
};
177+
161178
} // end namespace llvm
162179

163180
#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H

‎llvm/lib/Target/AMDGPU/CMakeLists.txt

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,6 @@ add_llvm_target(AMDGPUCodeGen
5151
AMDGPUAtomicOptimizer.cpp
5252
AMDGPUAttributor.cpp
5353
AMDGPUCallLowering.cpp
54-
AMDGPUCodeGenPassBuilder.cpp
5554
AMDGPUCodeGenPrepare.cpp
5655
AMDGPUCombinerHelper.cpp
5756
AMDGPUCtorDtorLowering.cpp

‎llvm/lib/Target/AMDGPU/R600TargetMachine.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,6 @@
1313
//===----------------------------------------------------------------------===//
1414

1515
#include "R600TargetMachine.h"
16-
#include "AMDGPUTargetMachine.h"
1716
#include "R600.h"
1817
#include "R600CodeGenPassBuilder.h"
1918
#include "R600MachineScheduler.h"

‎llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

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Original file line numberDiff line numberDiff line change
@@ -8,7 +8,6 @@
88

99
#include "SIMachineFunctionInfo.h"
1010
#include "AMDGPUSubtarget.h"
11-
#include "AMDGPUTargetMachine.h"
1211
#include "GCNSubtarget.h"
1312
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
1413
#include "SIRegisterInfo.h"

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