Renamed SLLISRLIFusion into ShiftedZExtFusion.

Added pseudocode to explain fusions.
Replace the "spacer" `ADDI` in the test with `XORI`- it was
confusing in case of LDADD fusion.

Author: mgudim

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -973,12 +973,12 @@ def TuneLUIADDIFusion
 def TuneAUIPCADDIFusion
     : SubtargetFeature<"auipc-addi-fusion", "HasAUIPCADDIFusion",
                        "true", "Enable AUIPC+ADDI macrofusion">;
-def TuneSLLISRLIFusion
-    : SubtargetFeature<"slli-srli-fusion", "HasSLLISRLIFusion",
-                       "true", "Enable SLLI+SRLI macrofusion">;
+def TuneShiftedZExtFusion
+    : SubtargetFeature<"shifted-zext-fusion", "HasShiftedZExtFusion",
+                       "true", "Enable SLLI+SRLI to be fused when computing (shifted) zero extension">;
 def TuneLDADDFusion
     : SubtargetFeature<"ld-add-fusion", "HasLDADDFusion",
-                       "true", "Enable fusion of load with the last instruction of the address calculation">;
+                       "true", "Enable LD+ADD macrofusion.">;
 
 def TuneNoDefaultUnroll
     : SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false",
@@ -1001,7 +1001,7 @@ def TuneVeyronFusions : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "V
                                          "Ventana Veyron-Series processors",
                                          [TuneLUIADDIFusion,
                                           TuneAUIPCADDIFusion,
-                                          TuneSLLISRLIFusion,
+                                          TuneShiftedZExtFusion,
                                           TuneLDADDFusion]>;
 
 // Assume that lock-free native-width atomics are available, even if the target

llvm/lib/Target/RISCV/RISCVMacroFusion.cpp

@@ -34,7 +34,9 @@ static bool checkRegisters(Register FirstDest, const MachineInstr &SecondMI) {
   return SecondMI.getOperand(0).getReg() == FirstDest;
 }
 
-// Fuse Load
+// Fuse load with add:
+// add rd, rs1, rs2
+// ld rd, 0(rd)
 static bool isLDADD(const MachineInstr *FirstMI, const MachineInstr &SecondMI) {
   if (SecondMI.getOpcode() != RISCV::LD)
     return false;
@@ -58,16 +60,16 @@ static bool isLDADD(const MachineInstr *FirstMI, const MachineInstr &SecondMI) {
 
 // Fuse these patterns:
 //
-// $rd = slli $rs0, 32
-// $rd = srli $rs1, x
+// slli rd, rs1, 32
+// srli rd, rd, x
 // where 0 <= x <= 32
 //
 // and
 //
-// $rd = slli $rs0, 48
-// $rd = srli $rs1, 48
-static bool isSLLISRLI(const MachineInstr *FirstMI,
-                       const MachineInstr &SecondMI) {
+// slli rd, rs1, 48
+// srli rd, rd, x
+static bool isShiftedZExt(const MachineInstr *FirstMI,
+                          const MachineInstr &SecondMI) {
   if (SecondMI.getOpcode() != RISCV::SRLI)
     return false;
 
@@ -95,6 +97,8 @@ static bool isSLLISRLI(const MachineInstr *FirstMI,
 }
 
 // Fuse AUIPC followed by ADDI
+// auipc rd, imm20
+// addi rd, rd, imm12
 static bool isAUIPCADDI(const MachineInstr *FirstMI,
                         const MachineInstr &SecondMI) {
   if (SecondMI.getOpcode() != RISCV::ADDI)
@@ -140,7 +144,7 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
   if (ST.hasAUIPCADDIFusion() && isAUIPCADDI(FirstMI, SecondMI))
     return true;
 
-  if (ST.hasSLLISRLIFusion() && isSLLISRLI(FirstMI, SecondMI))
+  if (ST.hasShiftedZExtFusion() && isShiftedZExt(FirstMI, SecondMI))
     return true;
 
   if (ST.hasLDADDFusion() && isLDADD(FirstMI, SecondMI))

llvm/lib/Target/RISCV/RISCVSubtarget.h

@@ -193,8 +193,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   }
 
   bool hasMacroFusion() const {
-    return hasLUIADDIFusion() || hasAUIPCADDIFusion() || hasSLLISRLIFusion() ||
-           hasLDADDFusion();
+    return hasLUIADDIFusion() || hasAUIPCADDIFusion() ||
+           hasShiftedZExtFusion() || hasLDADDFusion();
   }
 
   // Vector codegen related methods.

llvm/test/CodeGen/RISCV/macro-fusions-veyron-v1.mir

@@ -1,7 +1,7 @@
 # REQUIRES: asserts
 # RUN: llc -mtriple=riscv64-linux-gnu  -mcpu=veyron-v1 -x=mir < %s \
 # RUN:   -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \
-# RUN:   -mattr=+lui-addi-fusion,+auipc-addi-fusion,+slli-srli-fusion,+ld-add-fusion \
+# RUN:   -mattr=+lui-addi-fusion,+auipc-addi-fusion,+shifted-zext-fusion,+ld-add-fusion \
 # RUN:   | FileCheck %s
 
 # CHECK: lui_addi:%bb.0
@@ -14,7 +14,7 @@ body:             |
     liveins: $x10
     %1:gpr = COPY $x10
     %2:gpr = LUI 1
-    %3:gpr = ADDI %1, 2
+    %3:gpr = XORI %1, 2
     %4:gpr = ADDI %2, 3
     $x10 = COPY %3
     $x11 = COPY %4
@@ -31,7 +31,7 @@ body:             |
     liveins: $x10
     %1:gpr = COPY $x10
     %2:gpr = AUIPC 1
-    %3:gpr = ADDI %1, 2
+    %3:gpr = XORI %1, 2
     %4:gpr = ADDI %2, 3
     $x10 = COPY %3
     $x11 = COPY %4
@@ -48,7 +48,7 @@ body:             |
     liveins: $x10
     %1:gpr = COPY $x10
     %2:gpr = SLLI %1, 32
-    %3:gpr = ADDI %1, 3
+    %3:gpr = XORI %1, 3
     %4:gpr = SRLI %2, 4
     $x10 = COPY %3
     $x11 = COPY %4
@@ -65,7 +65,7 @@ body:             |
     liveins: $x10
     %1:gpr = COPY $x10
     %2:gpr = SLLI %1, 48
-    %3:gpr = ADDI %1, 3
+    %3:gpr = XORI %1, 3
     %4:gpr = SRLI %2, 48
     $x10 = COPY %3
     $x11 = COPY %4
@@ -82,7 +82,7 @@ body:             |
     liveins: $x10
     %1:gpr = COPY $x10
     %2:gpr = SLLI %1, 32
-    %3:gpr = ADDI %1, 3
+    %3:gpr = XORI %1, 3
     %4:gpr = SRLI %2, 33
     $x10 = COPY %3
     $x11 = COPY %4
@@ -99,7 +99,7 @@ body:             |
     liveins: $x10
     %1:gpr = COPY $x10
     %2:gpr = SLLI %1, 48
-    %3:gpr = ADDI %1, 3
+    %3:gpr = XORI %1, 3
     %4:gpr = SRLI %2, 4
     $x10 = COPY %3
     $x11 = COPY %4
@@ -116,7 +116,7 @@ body:             |
     liveins: $x10
     %1:gpr = COPY $x10
     %2:gpr = SLLI %1, 31
-    %3:gpr = ADDI %1, 3
+    %3:gpr = XORI %1, 3
     %4:gpr = SRLI %2, 4
     $x10 = COPY %3
     $x11 = COPY %4
@@ -133,7 +133,7 @@ body:             |
     liveins: $x10
     %1:gpr = COPY $x10
     %2:gpr = SLLI %1, 31
-    %3:gpr = ADDI %1, 3
+    %3:gpr = XORI %1, 3
     %4:gpr = SRLI %2, 48
     $x10 = COPY %3
     $x11 = COPY %4
@@ -151,7 +151,7 @@ body:             |
     %1:gpr = COPY $x10
     %2:gpr = COPY $x11
     %3:gpr = ADD %1, %2
-    %4:gpr = ADDI %2, 3
+    %4:gpr = XORI %2, 3
     %5:gpr = LD %3, 0
     $x10 = COPY %4
     $x11 = COPY %5