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[RISCV] Make fixed-point instructions commutable
This PR includes: * vsadd.vv/vsaddu.vv * vaadd.vv/vaaddu.vv * vsmul.vv
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3 files changed

+23
-18
lines changed

3 files changed

+23
-18
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2866,6 +2866,11 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
28662866
case CASE_RVV_OPCODE_WIDEN(VWMACC_VV):
28672867
case CASE_RVV_OPCODE_WIDEN(VWMACCU_VV):
28682868
case CASE_RVV_OPCODE_UNMASK(VADC_VVM):
2869+
case CASE_RVV_OPCODE(VSADD_VV):
2870+
case CASE_RVV_OPCODE(VSADDU_VV):
2871+
case CASE_RVV_OPCODE(VAADD_VV):
2872+
case CASE_RVV_OPCODE(VAADDU_VV):
2873+
case CASE_RVV_OPCODE(VSMUL_VV):
28692874
// Operands 2 and 3 are commutable.
28702875
return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
28712876
case CASE_VFMA_SPLATS(FMADD):

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2146,8 +2146,9 @@ multiclass VPseudoBinaryRoundingMode<VReg RetClass,
21462146
string Constraint = "",
21472147
int sew = 0,
21482148
int UsesVXRM = 1,
2149-
int TargetConstraintType = 1> {
2150-
let VLMul = MInfo.value, SEW=sew in {
2149+
int TargetConstraintType = 1,
2150+
bit Commutable = 0> {
2151+
let VLMul = MInfo.value, SEW=sew, isCommutable = Commutable in {
21512152
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
21522153
def suffix : VPseudoBinaryNoMaskRoundingMode<RetClass, Op1Class, Op2Class,
21532154
Constraint, UsesVXRM,
@@ -2232,8 +2233,9 @@ multiclass VPseudoBinaryV_VV<LMULInfo m, string Constraint = "", int sew = 0, bi
22322233
defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint, sew, Commutable=Commutable>;
22332234
}
22342235

2235-
multiclass VPseudoBinaryV_VV_RM<LMULInfo m, string Constraint = ""> {
2236-
defm _VV : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
2236+
multiclass VPseudoBinaryV_VV_RM<LMULInfo m, string Constraint = "", bit Commutable = 0> {
2237+
defm _VV : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, m.vrclass, m, Constraint,
2238+
Commutable=Commutable>;
22372239
}
22382240

22392241
// Similar to VPseudoBinaryV_VV, but uses MxListF.
@@ -2718,7 +2720,7 @@ multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = "">
27182720
multiclass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
27192721
foreach m = MxList in {
27202722
defvar mx = m.MX;
2721-
defm "" : VPseudoBinaryV_VV<m, Constraint>,
2723+
defm "" : VPseudoBinaryV_VV<m, Constraint, Commutable=1>,
27222724
SchedBinary<"WriteVSALUV", "ReadVSALUV", "ReadVSALUX", mx,
27232725
forceMergeOpRead=true>;
27242726
defm "" : VPseudoBinaryV_VX<m, Constraint>,
@@ -2788,7 +2790,7 @@ multiclass VPseudoVSALU_VV_VX {
27882790
multiclass VPseudoVSMUL_VV_VX_RM {
27892791
foreach m = MxList in {
27902792
defvar mx = m.MX;
2791-
defm "" : VPseudoBinaryV_VV_RM<m>,
2793+
defm "" : VPseudoBinaryV_VV_RM<m, Commutable=1>,
27922794
SchedBinary<"WriteVSMulV", "ReadVSMulV", "ReadVSMulV", mx,
27932795
forceMergeOpRead=true>;
27942796
defm "" : VPseudoBinaryV_VX_RM<m>,
@@ -2797,10 +2799,10 @@ multiclass VPseudoVSMUL_VV_VX_RM {
27972799
}
27982800
}
27992801

2800-
multiclass VPseudoVAALU_VV_VX_RM {
2802+
multiclass VPseudoVAALU_VV_VX_RM<bit Commutable = 0> {
28012803
foreach m = MxList in {
28022804
defvar mx = m.MX;
2803-
defm "" : VPseudoBinaryV_VV_RM<m>,
2805+
defm "" : VPseudoBinaryV_VV_RM<m, Commutable=Commutable>,
28042806
SchedBinary<"WriteVAALUV", "ReadVAALUV", "ReadVAALUV", mx,
28052807
forceMergeOpRead=true>;
28062808
defm "" : VPseudoBinaryV_VX_RM<m>,
@@ -6457,8 +6459,8 @@ let Defs = [VXSAT], hasSideEffects = 1 in {
64576459
//===----------------------------------------------------------------------===//
64586460
// 12.2. Vector Single-Width Averaging Add and Subtract
64596461
//===----------------------------------------------------------------------===//
6460-
defm PseudoVAADDU : VPseudoVAALU_VV_VX_RM;
6461-
defm PseudoVAADD : VPseudoVAALU_VV_VX_RM;
6462+
defm PseudoVAADDU : VPseudoVAALU_VV_VX_RM<Commutable=1>;
6463+
defm PseudoVAADD : VPseudoVAALU_VV_VX_RM<Commutable=1>;
64626464
defm PseudoVASUBU : VPseudoVAALU_VV_VX_RM;
64636465
defm PseudoVASUB : VPseudoVAALU_VV_VX_RM;
64646466

‎llvm/test/CodeGen/RISCV/rvv/commutable.ll

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -724,10 +724,9 @@ define <vscale x 1 x i64> @commutable_vaadd_vv(<vscale x 1 x i64> %0, <vscale x
724724
; CHECK: # %bb.0: # %entry
725725
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
726726
; CHECK-NEXT: csrwi vxrm, 0
727-
; CHECK-NEXT: vaadd.vv v10, v8, v9
728-
; CHECK-NEXT: vaadd.vv v8, v9, v8
727+
; CHECK-NEXT: vaadd.vv v8, v8, v9
729728
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
730-
; CHECK-NEXT: vadd.vv v8, v10, v8
729+
; CHECK-NEXT: vadd.vv v8, v8, v8
731730
; CHECK-NEXT: ret
732731
entry:
733732
%a = call <vscale x 1 x i64> @llvm.riscv.vaadd.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen 0, iXLen %2)
@@ -743,7 +742,7 @@ define <vscale x 1 x i64> @commutable_vaadd_vv_masked(<vscale x 1 x i64> %0, <vs
743742
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
744743
; CHECK-NEXT: csrwi vxrm, 0
745744
; CHECK-NEXT: vaadd.vv v10, v8, v9, v0.t
746-
; CHECK-NEXT: vaadd.vv v8, v9, v8, v0.t
745+
; CHECK-NEXT: vaadd.vv v8, v8, v9, v0.t
747746
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
748747
; CHECK-NEXT: vadd.vv v8, v10, v8
749748
; CHECK-NEXT: ret
@@ -760,10 +759,9 @@ define <vscale x 1 x i64> @commutable_vaaddu_vv(<vscale x 1 x i64> %0, <vscale x
760759
; CHECK: # %bb.0: # %entry
761760
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
762761
; CHECK-NEXT: csrwi vxrm, 0
763-
; CHECK-NEXT: vaaddu.vv v10, v8, v9
764-
; CHECK-NEXT: vaaddu.vv v8, v9, v8
762+
; CHECK-NEXT: vaaddu.vv v8, v8, v9
765763
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
766-
; CHECK-NEXT: vadd.vv v8, v10, v8
764+
; CHECK-NEXT: vadd.vv v8, v8, v8
767765
; CHECK-NEXT: ret
768766
entry:
769767
%a = call <vscale x 1 x i64> @llvm.riscv.vaaddu.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen 0, iXLen %2)
@@ -779,7 +777,7 @@ define <vscale x 1 x i64> @commutable_vaaddu_vv_masked(<vscale x 1 x i64> %0, <v
779777
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
780778
; CHECK-NEXT: csrwi vxrm, 0
781779
; CHECK-NEXT: vaaddu.vv v10, v8, v9, v0.t
782-
; CHECK-NEXT: vaaddu.vv v8, v9, v8, v0.t
780+
; CHECK-NEXT: vaaddu.vv v8, v8, v9, v0.t
783781
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
784782
; CHECK-NEXT: vadd.vv v8, v10, v8
785783
; CHECK-NEXT: ret

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