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[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
This wasn't scalable and made the RISCVCC enum effectively just a different way of spelling the branch opcodes. This patch reduces RISCVCC back down to 6 enum values. The primary user is select pseudoinstructions which now share the same encoding across all vendor extensions. The select opcode and condition code are used to determine the branch opcode when expanding the pseudo. The Cond SmallVector returned by analyzeBranch now returns the opcode instead of the RISCVCC. reverseBranchCondition now works directly on opcodes. getOppositeBranchCondition is also retained. Stacked on #145622
1 parent a6e5242 commit c824325

8 files changed

+180
-177
lines changed

‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -194,7 +194,7 @@ bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
194194
CC = RISCVCC::getOppositeBranchCondition(CC);
195195

196196
// Insert branch instruction.
197-
BuildMI(MBB, MBBI, DL, TII->getBrCond(CC))
197+
BuildMI(MBB, MBBI, DL, TII->get(RISCVCC::getBrCond(CC)))
198198
.addReg(MI.getOperand(1).getReg())
199199
.addReg(MI.getOperand(2).getReg())
200200
.addMBB(MergeBB);

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -21376,7 +21376,7 @@ EmitLoweredCascadedSelect(MachineInstr &First, MachineInstr &Second,
2137621376
Register FLHS = First.getOperand(1).getReg();
2137721377
Register FRHS = First.getOperand(2).getReg();
2137821378
// Insert appropriate branch.
21379-
BuildMI(FirstMBB, DL, TII.getBrCond(FirstCC))
21379+
BuildMI(FirstMBB, DL, TII.get(RISCVCC::getBrCond(FirstCC, First.getOpcode())))
2138021380
.addReg(FLHS)
2138121381
.addReg(FRHS)
2138221382
.addMBB(SinkMBB);
@@ -21388,7 +21388,8 @@ EmitLoweredCascadedSelect(MachineInstr &First, MachineInstr &Second,
2138821388

2138921389
auto SecondCC = static_cast<RISCVCC::CondCode>(Second.getOperand(3).getImm());
2139021390
// Insert appropriate branch.
21391-
BuildMI(ThisMBB, DL, TII.getBrCond(SecondCC))
21391+
BuildMI(ThisMBB, DL,
21392+
TII.get(RISCVCC::getBrCond(SecondCC, Second.getOpcode())))
2139221393
.addReg(SLHS)
2139321394
.addReg(SRHS)
2139421395
.addMBB(SinkMBB);
@@ -21527,12 +21528,12 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
2152721528

2152821529
// Insert appropriate branch.
2152921530
if (MI.getOperand(2).isImm())
21530-
BuildMI(HeadMBB, DL, TII.getBrCond(CC))
21531+
BuildMI(HeadMBB, DL, TII.get(RISCVCC::getBrCond(CC, MI.getOpcode())))
2153121532
.addReg(LHS)
2153221533
.addImm(MI.getOperand(2).getImm())
2153321534
.addMBB(TailMBB);
2153421535
else
21535-
BuildMI(HeadMBB, DL, TII.getBrCond(CC))
21536+
BuildMI(HeadMBB, DL, TII.get(RISCVCC::getBrCond(CC, MI.getOpcode())))
2153621537
.addReg(LHS)
2153721538
.addReg(RHS)
2153821539
.addMBB(TailMBB);

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 162 additions & 110 deletions
Original file line numberDiff line numberDiff line change
@@ -958,54 +958,41 @@ void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
958958
}
959959
}
960960

961-
static RISCVCC::CondCode getCondFromBranchOpc(unsigned Opc) {
961+
RISCVCC::CondCode RISCVInstrInfo::getCondFromBranchOpc(unsigned Opc) {
962962
switch (Opc) {
963963
default:
964964
return RISCVCC::COND_INVALID;
965965
case RISCV::BEQ:
966-
return RISCVCC::COND_EQ;
967-
case RISCV::BNE:
968-
return RISCVCC::COND_NE;
969-
case RISCV::BLT:
970-
return RISCVCC::COND_LT;
971-
case RISCV::BGE:
972-
return RISCVCC::COND_GE;
973-
case RISCV::BLTU:
974-
return RISCVCC::COND_LTU;
975-
case RISCV::BGEU:
976-
return RISCVCC::COND_GEU;
977966
case RISCV::CV_BEQIMM:
978-
return RISCVCC::COND_CV_BEQIMM;
979-
case RISCV::CV_BNEIMM:
980-
return RISCVCC::COND_CV_BNEIMM;
981967
case RISCV::QC_BEQI:
982-
return RISCVCC::COND_QC_BEQI;
983968
case RISCV::QC_E_BEQI:
984-
return RISCVCC::COND_QC_E_BEQI;
969+
return RISCVCC::COND_EQ;
970+
case RISCV::BNE:
985971
case RISCV::QC_BNEI:
986-
return RISCVCC::COND_QC_BNEI;
987972
case RISCV::QC_E_BNEI:
988-
return RISCVCC::COND_QC_E_BNEI;
973+
case RISCV::CV_BNEIMM:
974+
return RISCVCC::COND_NE;
975+
case RISCV::BLT:
989976
case RISCV::QC_BLTI:
990-
return RISCVCC::COND_QC_BLTI;
991977
case RISCV::QC_E_BLTI:
992-
return RISCVCC::COND_QC_E_BLTI;
978+
return RISCVCC::COND_LT;
979+
case RISCV::BGE:
993980
case RISCV::QC_BGEI:
994-
return RISCVCC::COND_QC_BGEI;
995981
case RISCV::QC_E_BGEI:
996-
return RISCVCC::COND_QC_E_BGEI;
982+
return RISCVCC::COND_GE;
983+
case RISCV::BLTU:
997984
case RISCV::QC_BLTUI:
998-
return RISCVCC::COND_QC_BLTUI;
999985
case RISCV::QC_E_BLTUI:
1000-
return RISCVCC::COND_QC_E_BLTUI;
986+
return RISCVCC::COND_LTU;
987+
case RISCV::BGEU:
1001988
case RISCV::QC_BGEUI:
1002-
return RISCVCC::COND_QC_BGEUI;
1003989
case RISCV::QC_E_BGEUI:
1004-
return RISCVCC::COND_QC_E_BGEUI;
990+
return RISCVCC::COND_GEU;
1005991
}
1006992
}
1007993

1008-
bool RISCVInstrInfo::evaluateCondBranch(unsigned CC, int64_t C0, int64_t C1) {
994+
bool RISCVInstrInfo::evaluateCondBranch(RISCVCC::CondCode CC, int64_t C0,
995+
int64_t C1) {
1009996
switch (CC) {
1010997
default:
1011998
llvm_unreachable("Unexpected CC");
@@ -1033,63 +1020,92 @@ static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
10331020
assert(LastInst.getDesc().isConditionalBranch() &&
10341021
"Unknown conditional branch");
10351022
Target = LastInst.getOperand(2).getMBB();
1036-
unsigned CC = getCondFromBranchOpc(LastInst.getOpcode());
1037-
Cond.push_back(MachineOperand::CreateImm(CC));
1023+
Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
10381024
Cond.push_back(LastInst.getOperand(0));
10391025
Cond.push_back(LastInst.getOperand(1));
10401026
}
10411027

1042-
unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC) {
1043-
switch (CC) {
1028+
unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC, unsigned SelectOpc) {
1029+
switch (SelectOpc) {
10441030
default:
1045-
llvm_unreachable("Unknown condition code!");
1046-
case RISCVCC::COND_EQ:
1047-
return RISCV::BEQ;
1048-
case RISCVCC::COND_NE:
1049-
return RISCV::BNE;
1050-
case RISCVCC::COND_LT:
1051-
return RISCV::BLT;
1052-
case RISCVCC::COND_GE:
1053-
return RISCV::BGE;
1054-
case RISCVCC::COND_LTU:
1055-
return RISCV::BLTU;
1056-
case RISCVCC::COND_GEU:
1057-
return RISCV::BGEU;
1058-
case RISCVCC::COND_CV_BEQIMM:
1059-
return RISCV::CV_BEQIMM;
1060-
case RISCVCC::COND_CV_BNEIMM:
1061-
return RISCV::CV_BNEIMM;
1062-
case RISCVCC::COND_QC_BEQI:
1063-
return RISCV::QC_BEQI;
1064-
case RISCVCC::COND_QC_E_BEQI:
1065-
return RISCV::QC_E_BEQI;
1066-
case RISCVCC::COND_QC_BNEI:
1067-
return RISCV::QC_BNEI;
1068-
case RISCVCC::COND_QC_E_BNEI:
1069-
return RISCV::QC_E_BNEI;
1070-
case RISCVCC::COND_QC_BLTI:
1071-
return RISCV::QC_BLTI;
1072-
case RISCVCC::COND_QC_E_BLTI:
1073-
return RISCV::QC_E_BLTI;
1074-
case RISCVCC::COND_QC_BGEI:
1075-
return RISCV::QC_BGEI;
1076-
case RISCVCC::COND_QC_E_BGEI:
1077-
return RISCV::QC_E_BGEI;
1078-
case RISCVCC::COND_QC_BLTUI:
1079-
return RISCV::QC_BLTUI;
1080-
case RISCVCC::COND_QC_E_BLTUI:
1081-
return RISCV::QC_E_BLTUI;
1082-
case RISCVCC::COND_QC_BGEUI:
1083-
return RISCV::QC_BGEUI;
1084-
case RISCVCC::COND_QC_E_BGEUI:
1085-
return RISCV::QC_E_BGEUI;
1031+
switch (CC) {
1032+
default:
1033+
llvm_unreachable("Unexpected condition code!");
1034+
case RISCVCC::COND_EQ:
1035+
return RISCV::BEQ;
1036+
case RISCVCC::COND_NE:
1037+
return RISCV::BNE;
1038+
case RISCVCC::COND_LT:
1039+
return RISCV::BLT;
1040+
case RISCVCC::COND_GE:
1041+
return RISCV::BGE;
1042+
case RISCVCC::COND_LTU:
1043+
return RISCV::BLTU;
1044+
case RISCVCC::COND_GEU:
1045+
return RISCV::BGEU;
1046+
}
1047+
break;
1048+
case RISCV::Select_GPR_Using_CC_SImm5_CV:
1049+
switch (CC) {
1050+
default:
1051+
llvm_unreachable("Unexpected condition code!");
1052+
case RISCVCC::COND_EQ:
1053+
return RISCV::CV_BEQIMM;
1054+
case RISCVCC::COND_NE:
1055+
return RISCV::CV_BNEIMM;
1056+
}
1057+
break;
1058+
case RISCV::Select_GPRNoX0_Using_CC_SImm5NonZero_QC:
1059+
switch (CC) {
1060+
default:
1061+
llvm_unreachable("Unexpected condition code!");
1062+
case RISCVCC::COND_EQ:
1063+
return RISCV::QC_BEQI;
1064+
case RISCVCC::COND_NE:
1065+
return RISCV::QC_BNEI;
1066+
case RISCVCC::COND_LT:
1067+
return RISCV::QC_BLTI;
1068+
case RISCVCC::COND_GE:
1069+
return RISCV::QC_BGEI;
1070+
}
1071+
break;
1072+
case RISCV::Select_GPRNoX0_Using_CC_UImm5NonZero_QC:
1073+
switch (CC) {
1074+
default:
1075+
llvm_unreachable("Unexpected condition code!");
1076+
case RISCVCC::COND_LTU:
1077+
return RISCV::QC_BLTUI;
1078+
case RISCVCC::COND_GEU:
1079+
return RISCV::QC_BGEUI;
1080+
}
1081+
break;
1082+
case RISCV::Select_GPRNoX0_Using_CC_SImm16NonZero_QC:
1083+
switch (CC) {
1084+
default:
1085+
llvm_unreachable("Unexpected condition code!");
1086+
case RISCVCC::COND_EQ:
1087+
return RISCV::QC_E_BEQI;
1088+
case RISCVCC::COND_NE:
1089+
return RISCV::QC_E_BNEI;
1090+
case RISCVCC::COND_LT:
1091+
return RISCV::QC_E_BLTI;
1092+
case RISCVCC::COND_GE:
1093+
return RISCV::QC_E_BGEI;
1094+
}
1095+
break;
1096+
case RISCV::Select_GPRNoX0_Using_CC_UImm16NonZero_QC:
1097+
switch (CC) {
1098+
default:
1099+
llvm_unreachable("Unexpected condition code!");
1100+
case RISCVCC::COND_LTU:
1101+
return RISCV::QC_E_BLTUI;
1102+
case RISCVCC::COND_GEU:
1103+
return RISCV::QC_E_BGEUI;
1104+
}
1105+
break;
10861106
}
10871107
}
10881108

1089-
const MCInstrDesc &RISCVInstrInfo::getBrCond(RISCVCC::CondCode CC) const {
1090-
return get(RISCVCC::getBrCond(CC));
1091-
}
1092-
10931109
RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) {
10941110
switch (CC) {
10951111
default:
@@ -1106,34 +1122,6 @@ RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) {
11061122
return RISCVCC::COND_GEU;
11071123
case RISCVCC::COND_GEU:
11081124
return RISCVCC::COND_LTU;
1109-
case RISCVCC::COND_CV_BEQIMM:
1110-
return RISCVCC::COND_CV_BNEIMM;
1111-
case RISCVCC::COND_CV_BNEIMM:
1112-
return RISCVCC::COND_CV_BEQIMM;
1113-
case RISCVCC::COND_QC_BEQI:
1114-
return RISCVCC::COND_QC_BNEI;
1115-
case RISCVCC::COND_QC_E_BEQI:
1116-
return RISCVCC::COND_QC_E_BNEI;
1117-
case RISCVCC::COND_QC_BNEI:
1118-
return RISCVCC::COND_QC_BEQI;
1119-
case RISCVCC::COND_QC_E_BNEI:
1120-
return RISCVCC::COND_QC_E_BEQI;
1121-
case RISCVCC::COND_QC_BLTI:
1122-
return RISCVCC::COND_QC_BGEI;
1123-
case RISCVCC::COND_QC_E_BLTI:
1124-
return RISCVCC::COND_QC_E_BGEI;
1125-
case RISCVCC::COND_QC_BGEI:
1126-
return RISCVCC::COND_QC_BLTI;
1127-
case RISCVCC::COND_QC_E_BGEI:
1128-
return RISCVCC::COND_QC_E_BLTI;
1129-
case RISCVCC::COND_QC_BLTUI:
1130-
return RISCVCC::COND_QC_BGEUI;
1131-
case RISCVCC::COND_QC_E_BLTUI:
1132-
return RISCVCC::COND_QC_E_BGEUI;
1133-
case RISCVCC::COND_QC_BGEUI:
1134-
return RISCVCC::COND_QC_BLTUI;
1135-
case RISCVCC::COND_QC_E_BGEUI:
1136-
return RISCVCC::COND_QC_E_BLTUI;
11371125
}
11381126
}
11391127

@@ -1263,9 +1251,10 @@ unsigned RISCVInstrInfo::insertBranch(
12631251
}
12641252

12651253
// Either a one or two-way conditional branch.
1266-
auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm());
1267-
MachineInstr &CondMI =
1268-
*BuildMI(&MBB, DL, getBrCond(CC)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
1254+
MachineInstr &CondMI = *BuildMI(&MBB, DL, get(Cond[0].getImm()))
1255+
.add(Cond[1])
1256+
.add(Cond[2])
1257+
.addMBB(TBB);
12691258
if (BytesAdded)
12701259
*BytesAdded += getInstSizeInBytes(CondMI);
12711260

@@ -1348,8 +1337,71 @@ void RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
13481337
bool RISCVInstrInfo::reverseBranchCondition(
13491338
SmallVectorImpl<MachineOperand> &Cond) const {
13501339
assert((Cond.size() == 3) && "Invalid branch condition!");
1351-
auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm());
1352-
Cond[0].setImm(getOppositeBranchCondition(CC));
1340+
switch (Cond[0].getImm()) {
1341+
default:
1342+
llvm_unreachable("Unknown conditional branch!");
1343+
case RISCV::BEQ:
1344+
Cond[0].setImm(RISCV::BNE);
1345+
break;
1346+
case RISCV::BNE:
1347+
Cond[0].setImm(RISCV::BEQ);
1348+
break;
1349+
case RISCV::BLT:
1350+
Cond[0].setImm(RISCV::BGE);
1351+
break;
1352+
case RISCV::BGE:
1353+
Cond[0].setImm(RISCV::BLT);
1354+
break;
1355+
case RISCV::BLTU:
1356+
Cond[0].setImm(RISCV::BGEU);
1357+
break;
1358+
case RISCV::BGEU:
1359+
Cond[0].setImm(RISCV::BLTU);
1360+
break;
1361+
case RISCV::CV_BEQIMM:
1362+
Cond[0].setImm(RISCV::CV_BNEIMM);
1363+
break;
1364+
case RISCV::CV_BNEIMM:
1365+
Cond[0].setImm(RISCV::CV_BEQIMM);
1366+
break;
1367+
case RISCV::QC_BEQI:
1368+
Cond[0].setImm(RISCV::QC_BNEI);
1369+
break;
1370+
case RISCV::QC_BNEI:
1371+
Cond[0].setImm(RISCV::QC_BEQI);
1372+
break;
1373+
case RISCV::QC_BGEI:
1374+
Cond[0].setImm(RISCV::QC_BLTI);
1375+
break;
1376+
case RISCV::QC_BLTI:
1377+
Cond[0].setImm(RISCV::QC_BGEI);
1378+
break;
1379+
case RISCV::QC_BGEUI:
1380+
Cond[0].setImm(RISCV::QC_BLTUI);
1381+
break;
1382+
case RISCV::QC_BLTUI:
1383+
Cond[0].setImm(RISCV::QC_BGEUI);
1384+
break;
1385+
case RISCV::QC_E_BEQI:
1386+
Cond[0].setImm(RISCV::QC_E_BNEI);
1387+
break;
1388+
case RISCV::QC_E_BNEI:
1389+
Cond[0].setImm(RISCV::QC_E_BEQI);
1390+
break;
1391+
case RISCV::QC_E_BGEI:
1392+
Cond[0].setImm(RISCV::QC_E_BLTI);
1393+
break;
1394+
case RISCV::QC_E_BLTI:
1395+
Cond[0].setImm(RISCV::QC_E_BGEI);
1396+
break;
1397+
case RISCV::QC_E_BGEUI:
1398+
Cond[0].setImm(RISCV::QC_E_BLTUI);
1399+
break;
1400+
case RISCV::QC_E_BLTUI:
1401+
Cond[0].setImm(RISCV::QC_E_BGEUI);
1402+
break;
1403+
}
1404+
13531405
return false;
13541406
}
13551407

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