[RISCV] Remove separate immediate condition codes from RISCVCC. NFC #145762
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesThis wasn't scalable and made the RISCVCC enum effectively just This patch reduces RISCVCC back down to 6 enum values. The primary user The Cond SmallVector returned by analyzeBranch now returns the opcode Patch is 23.94 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/145762.diff 8 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index d3dce4edb1e75..3dc18cce45eff 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -194,7 +194,7 @@ bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
CC = RISCVCC::getOppositeBranchCondition(CC);
// Insert branch instruction.
- BuildMI(MBB, MBBI, DL, TII->getBrCond(CC))
+ BuildMI(MBB, MBBI, DL, TII->get(RISCVCC::getBrCond(CC)))
.addReg(MI.getOperand(1).getReg())
.addReg(MI.getOperand(2).getReg())
.addMBB(MergeBB);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 712f6154732a2..a9c98e46bb482 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21335,7 +21335,7 @@ EmitLoweredCascadedSelect(MachineInstr &First, MachineInstr &Second,
Register FLHS = First.getOperand(1).getReg();
Register FRHS = First.getOperand(2).getReg();
// Insert appropriate branch.
- BuildMI(FirstMBB, DL, TII.getBrCond(FirstCC))
+ BuildMI(FirstMBB, DL, TII.get(RISCVCC::getBrCond(FirstCC, First.getOpcode())))
.addReg(FLHS)
.addReg(FRHS)
.addMBB(SinkMBB);
@@ -21347,7 +21347,8 @@ EmitLoweredCascadedSelect(MachineInstr &First, MachineInstr &Second,
auto SecondCC = static_cast<RISCVCC::CondCode>(Second.getOperand(3).getImm());
// Insert appropriate branch.
- BuildMI(ThisMBB, DL, TII.getBrCond(SecondCC))
+ BuildMI(ThisMBB, DL,
+ TII.get(RISCVCC::getBrCond(SecondCC, Second.getOpcode())))
.addReg(SLHS)
.addReg(SRHS)
.addMBB(SinkMBB);
@@ -21486,12 +21487,12 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
// Insert appropriate branch.
if (MI.getOperand(2).isImm())
- BuildMI(HeadMBB, DL, TII.getBrCond(CC))
+ BuildMI(HeadMBB, DL, TII.get(RISCVCC::getBrCond(CC, MI.getOpcode())))
.addReg(LHS)
.addImm(MI.getOperand(2).getImm())
.addMBB(TailMBB);
else
- BuildMI(HeadMBB, DL, TII.getBrCond(CC))
+ BuildMI(HeadMBB, DL, TII.get(RISCVCC::getBrCond(CC, MI.getOpcode())))
.addReg(LHS)
.addReg(RHS)
.addMBB(TailMBB);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 5711f0077b12d..0b334b993218f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -958,54 +958,41 @@ void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
}
}
-static RISCVCC::CondCode getCondFromBranchOpc(unsigned Opc) {
+RISCVCC::CondCode RISCVInstrInfo::getCondFromBranchOpc(unsigned Opc) {
switch (Opc) {
default:
return RISCVCC::COND_INVALID;
case RISCV::BEQ:
- return RISCVCC::COND_EQ;
- case RISCV::BNE:
- return RISCVCC::COND_NE;
- case RISCV::BLT:
- return RISCVCC::COND_LT;
- case RISCV::BGE:
- return RISCVCC::COND_GE;
- case RISCV::BLTU:
- return RISCVCC::COND_LTU;
- case RISCV::BGEU:
- return RISCVCC::COND_GEU;
case RISCV::CV_BEQIMM:
- return RISCVCC::COND_CV_BEQIMM;
- case RISCV::CV_BNEIMM:
- return RISCVCC::COND_CV_BNEIMM;
case RISCV::QC_BEQI:
- return RISCVCC::COND_QC_BEQI;
case RISCV::QC_E_BEQI:
- return RISCVCC::COND_QC_E_BEQI;
+ return RISCVCC::COND_EQ;
+ case RISCV::BNE:
case RISCV::QC_BNEI:
- return RISCVCC::COND_QC_BNEI;
case RISCV::QC_E_BNEI:
- return RISCVCC::COND_QC_E_BNEI;
+ case RISCV::CV_BNEIMM:
+ return RISCVCC::COND_NE;
+ case RISCV::BLT:
case RISCV::QC_BLTI:
- return RISCVCC::COND_QC_BLTI;
case RISCV::QC_E_BLTI:
- return RISCVCC::COND_QC_E_BLTI;
+ return RISCVCC::COND_LT;
+ case RISCV::BGE:
case RISCV::QC_BGEI:
- return RISCVCC::COND_QC_BGEI;
case RISCV::QC_E_BGEI:
- return RISCVCC::COND_QC_E_BGEI;
+ return RISCVCC::COND_GE;
+ case RISCV::BLTU:
case RISCV::QC_BLTUI:
- return RISCVCC::COND_QC_BLTUI;
case RISCV::QC_E_BLTUI:
- return RISCVCC::COND_QC_E_BLTUI;
+ return RISCVCC::COND_LTU;
+ case RISCV::BGEU:
case RISCV::QC_BGEUI:
- return RISCVCC::COND_QC_BGEUI;
case RISCV::QC_E_BGEUI:
- return RISCVCC::COND_QC_E_BGEUI;
+ return RISCVCC::COND_GEU;
}
}
-bool RISCVInstrInfo::evaluateCondBranch(unsigned CC, int64_t C0, int64_t C1) {
+bool RISCVInstrInfo::evaluateCondBranch(RISCVCC::CondCode CC, int64_t C0,
+ int64_t C1) {
switch (CC) {
default:
llvm_unreachable("Unexpected CC");
@@ -1033,63 +1020,92 @@ static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
assert(LastInst.getDesc().isConditionalBranch() &&
"Unknown conditional branch");
Target = LastInst.getOperand(2).getMBB();
- unsigned CC = getCondFromBranchOpc(LastInst.getOpcode());
- Cond.push_back(MachineOperand::CreateImm(CC));
+ Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
Cond.push_back(LastInst.getOperand(0));
Cond.push_back(LastInst.getOperand(1));
}
-unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC) {
- switch (CC) {
+unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC, unsigned SelectOpc) {
+ switch (SelectOpc) {
default:
- llvm_unreachable("Unknown condition code!");
- case RISCVCC::COND_EQ:
- return RISCV::BEQ;
- case RISCVCC::COND_NE:
- return RISCV::BNE;
- case RISCVCC::COND_LT:
- return RISCV::BLT;
- case RISCVCC::COND_GE:
- return RISCV::BGE;
- case RISCVCC::COND_LTU:
- return RISCV::BLTU;
- case RISCVCC::COND_GEU:
- return RISCV::BGEU;
- case RISCVCC::COND_CV_BEQIMM:
- return RISCV::CV_BEQIMM;
- case RISCVCC::COND_CV_BNEIMM:
- return RISCV::CV_BNEIMM;
- case RISCVCC::COND_QC_BEQI:
- return RISCV::QC_BEQI;
- case RISCVCC::COND_QC_E_BEQI:
- return RISCV::QC_E_BEQI;
- case RISCVCC::COND_QC_BNEI:
- return RISCV::QC_BNEI;
- case RISCVCC::COND_QC_E_BNEI:
- return RISCV::QC_E_BNEI;
- case RISCVCC::COND_QC_BLTI:
- return RISCV::QC_BLTI;
- case RISCVCC::COND_QC_E_BLTI:
- return RISCV::QC_E_BLTI;
- case RISCVCC::COND_QC_BGEI:
- return RISCV::QC_BGEI;
- case RISCVCC::COND_QC_E_BGEI:
- return RISCV::QC_E_BGEI;
- case RISCVCC::COND_QC_BLTUI:
- return RISCV::QC_BLTUI;
- case RISCVCC::COND_QC_E_BLTUI:
- return RISCV::QC_E_BLTUI;
- case RISCVCC::COND_QC_BGEUI:
- return RISCV::QC_BGEUI;
- case RISCVCC::COND_QC_E_BGEUI:
- return RISCV::QC_E_BGEUI;
+ switch (CC) {
+ default:
+ llvm_unreachable("Unexpected condition code!");
+ case RISCVCC::COND_EQ:
+ return RISCV::BEQ;
+ case RISCVCC::COND_NE:
+ return RISCV::BNE;
+ case RISCVCC::COND_LT:
+ return RISCV::BLT;
+ case RISCVCC::COND_GE:
+ return RISCV::BGE;
+ case RISCVCC::COND_LTU:
+ return RISCV::BLTU;
+ case RISCVCC::COND_GEU:
+ return RISCV::BGEU;
+ }
+ break;
+ case RISCV::Select_GPR_Using_CC_SImm5_CV:
+ switch (CC) {
+ default:
+ llvm_unreachable("Unexpected condition code!");
+ case RISCVCC::COND_EQ:
+ return RISCV::CV_BEQIMM;
+ case RISCVCC::COND_NE:
+ return RISCV::CV_BNEIMM;
+ }
+ break;
+ case RISCV::Select_GPRNoX0_Using_CC_SImm5NonZero_QC:
+ switch (CC) {
+ default:
+ llvm_unreachable("Unexpected condition code!");
+ case RISCVCC::COND_EQ:
+ return RISCV::QC_BEQI;
+ case RISCVCC::COND_NE:
+ return RISCV::QC_BNEI;
+ case RISCVCC::COND_LT:
+ return RISCV::QC_BLTI;
+ case RISCVCC::COND_GE:
+ return RISCV::QC_BGEI;
+ }
+ break;
+ case RISCV::Select_GPRNoX0_Using_CC_UImm5NonZero_QC:
+ switch (CC) {
+ default:
+ llvm_unreachable("Unexpected condition code!");
+ case RISCVCC::COND_LTU:
+ return RISCV::QC_BLTUI;
+ case RISCVCC::COND_GEU:
+ return RISCV::QC_BGEUI;
+ }
+ break;
+ case RISCV::Select_GPRNoX0_Using_CC_SImm16NonZero_QC:
+ switch (CC) {
+ default:
+ llvm_unreachable("Unexpected condition code!");
+ case RISCVCC::COND_EQ:
+ return RISCV::QC_E_BEQI;
+ case RISCVCC::COND_NE:
+ return RISCV::QC_E_BNEI;
+ case RISCVCC::COND_LT:
+ return RISCV::QC_E_BLTI;
+ case RISCVCC::COND_GE:
+ return RISCV::QC_E_BGEI;
+ }
+ break;
+ case RISCV::Select_GPRNoX0_Using_CC_UImm16NonZero_QC:
+ switch (CC) {
+ default:
+ llvm_unreachable("Unexpected condition code!");
+ case RISCVCC::COND_LTU:
+ return RISCV::QC_E_BLTUI;
+ case RISCVCC::COND_GEU:
+ return RISCV::QC_E_BGEUI;
+ }
+ break;
}
}
-const MCInstrDesc &RISCVInstrInfo::getBrCond(RISCVCC::CondCode CC) const {
- return get(RISCVCC::getBrCond(CC));
-}
-
RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) {
switch (CC) {
default:
@@ -1106,34 +1122,6 @@ RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) {
return RISCVCC::COND_GEU;
case RISCVCC::COND_GEU:
return RISCVCC::COND_LTU;
- case RISCVCC::COND_CV_BEQIMM:
- return RISCVCC::COND_CV_BNEIMM;
- case RISCVCC::COND_CV_BNEIMM:
- return RISCVCC::COND_CV_BEQIMM;
- case RISCVCC::COND_QC_BEQI:
- return RISCVCC::COND_QC_BNEI;
- case RISCVCC::COND_QC_E_BEQI:
- return RISCVCC::COND_QC_E_BNEI;
- case RISCVCC::COND_QC_BNEI:
- return RISCVCC::COND_QC_BEQI;
- case RISCVCC::COND_QC_E_BNEI:
- return RISCVCC::COND_QC_E_BEQI;
- case RISCVCC::COND_QC_BLTI:
- return RISCVCC::COND_QC_BGEI;
- case RISCVCC::COND_QC_E_BLTI:
- return RISCVCC::COND_QC_E_BGEI;
- case RISCVCC::COND_QC_BGEI:
- return RISCVCC::COND_QC_BLTI;
- case RISCVCC::COND_QC_E_BGEI:
- return RISCVCC::COND_QC_E_BLTI;
- case RISCVCC::COND_QC_BLTUI:
- return RISCVCC::COND_QC_BGEUI;
- case RISCVCC::COND_QC_E_BLTUI:
- return RISCVCC::COND_QC_E_BGEUI;
- case RISCVCC::COND_QC_BGEUI:
- return RISCVCC::COND_QC_BLTUI;
- case RISCVCC::COND_QC_E_BGEUI:
- return RISCVCC::COND_QC_E_BLTUI;
}
}
@@ -1263,9 +1251,10 @@ unsigned RISCVInstrInfo::insertBranch(
}
// Either a one or two-way conditional branch.
- auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm());
- MachineInstr &CondMI =
- *BuildMI(&MBB, DL, getBrCond(CC)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
+ MachineInstr &CondMI = *BuildMI(&MBB, DL, get(Cond[0].getImm()))
+ .add(Cond[1])
+ .add(Cond[2])
+ .addMBB(TBB);
if (BytesAdded)
*BytesAdded += getInstSizeInBytes(CondMI);
@@ -1348,8 +1337,71 @@ void RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
bool RISCVInstrInfo::reverseBranchCondition(
SmallVectorImpl<MachineOperand> &Cond) const {
assert((Cond.size() == 3) && "Invalid branch condition!");
- auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm());
- Cond[0].setImm(getOppositeBranchCondition(CC));
+ switch (Cond[0].getImm()) {
+ default:
+ llvm_unreachable("Unknown conditional branch!");
+ case RISCV::BEQ:
+ Cond[0].setImm(RISCV::BNE);
+ break;
+ case RISCV::BNE:
+ Cond[0].setImm(RISCV::BEQ);
+ break;
+ case RISCV::BLT:
+ Cond[0].setImm(RISCV::BGE);
+ break;
+ case RISCV::BGE:
+ Cond[0].setImm(RISCV::BLT);
+ break;
+ case RISCV::BLTU:
+ Cond[0].setImm(RISCV::BGEU);
+ break;
+ case RISCV::BGEU:
+ Cond[0].setImm(RISCV::BLTU);
+ break;
+ case RISCV::CV_BEQIMM:
+ Cond[0].setImm(RISCV::CV_BNEIMM);
+ break;
+ case RISCV::CV_BNEIMM:
+ Cond[0].setImm(RISCV::CV_BEQIMM);
+ break;
+ case RISCV::QC_BEQI:
+ Cond[0].setImm(RISCV::QC_BNEI);
+ break;
+ case RISCV::QC_BNEI:
+ Cond[0].setImm(RISCV::QC_BEQI);
+ break;
+ case RISCV::QC_BGEI:
+ Cond[0].setImm(RISCV::QC_BLTI);
+ break;
+ case RISCV::QC_BLTI:
+ Cond[0].setImm(RISCV::QC_BGEI);
+ break;
+ case RISCV::QC_BGEUI:
+ Cond[0].setImm(RISCV::QC_BLTUI);
+ break;
+ case RISCV::QC_BLTUI:
+ Cond[0].setImm(RISCV::QC_BGEUI);
+ break;
+ case RISCV::QC_E_BEQI:
+ Cond[0].setImm(RISCV::QC_E_BNEI);
+ break;
+ case RISCV::QC_E_BNEI:
+ Cond[0].setImm(RISCV::QC_E_BEQI);
+ break;
+ case RISCV::QC_E_BGEI:
+ Cond[0].setImm(RISCV::QC_E_BLTI);
+ break;
+ case RISCV::QC_E_BLTI:
+ Cond[0].setImm(RISCV::QC_E_BGEI);
+ break;
+ case RISCV::QC_E_BGEUI:
+ Cond[0].setImm(RISCV::QC_E_BLTUI);
+ break;
+ case RISCV::QC_E_BLTUI:
+ Cond[0].setImm(RISCV::QC_E_BGEUI);
+ break;
+ }
+
return false;
}
@@ -1379,40 +1431,50 @@ bool RISCVInstrInfo::isFromLoadImm(const MachineRegisterInfo &MRI,
}
bool RISCVInstrInfo::optimizeCondBranch(MachineInstr &MI) const {
+ bool IsSigned = false;
+ bool IsEquality = false;
+ switch (MI.getOpcode()) {
+ default:
+ return false;
+ case RISCV::BEQ:
+ case RISCV::BNE:
+ IsEquality = true;
+ break;
+ case RISCV::BGE:
+ case RISCV::BLT:
+ IsSigned = true;
+ break;
+ case RISCV::BGEU:
+ case RISCV::BLTU:
+ break;
+ }
+
MachineBasicBlock *MBB = MI.getParent();
MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
- MachineBasicBlock *TBB, *FBB;
- SmallVector<MachineOperand, 3> Cond;
- if (analyzeBranch(*MBB, TBB, FBB, Cond, /*AllowModify=*/false))
- return false;
+ const MachineOperand &LHS = MI.getOperand(0);
+ const MachineOperand &RHS = MI.getOperand(1);
+ MachineBasicBlock *TBB = MI.getOperand(2).getMBB();
- RISCVCC::CondCode CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm());
+ RISCVCC::CondCode CC = getCondFromBranchOpc(MI.getOpcode());
assert(CC != RISCVCC::COND_INVALID);
- auto modifyBranch = [&]() {
- // Build the new branch and remove the old one.
- BuildMI(*MBB, MI, MI.getDebugLoc(),
- getBrCond(static_cast<RISCVCC::CondCode>(Cond[0].getImm())))
- .add(Cond[1])
- .add(Cond[2])
- .addMBB(TBB);
- MI.eraseFromParent();
- };
-
// Canonicalize conditional branches which can be constant folded into
// beqz or bnez. We can't modify the CFG here.
int64_t C0, C1;
- if (isFromLoadImm(MRI, Cond[1], C0) && isFromLoadImm(MRI, Cond[2], C1)) {
- unsigned NewCC =
- evaluateCondBranch(CC, C0, C1) ? RISCVCC::COND_EQ : RISCVCC::COND_NE;
- Cond[0] = MachineOperand::CreateImm(NewCC);
- Cond[1] = Cond[2] = MachineOperand::CreateReg(RISCV::X0, /*isDef=*/false);
- modifyBranch();
+ if (isFromLoadImm(MRI, LHS, C0) && isFromLoadImm(MRI, RHS, C1)) {
+ unsigned NewOpc = evaluateCondBranch(CC, C0, C1) ? RISCV::BEQ : RISCV::BNE;
+ MachineOperand Zero = MachineOperand::CreateReg(RISCV::X0, /*isDef=*/false);
+ // Build the new branch and remove the old one.
+ BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
+ .add(Zero)
+ .add(Zero)
+ .addMBB(TBB);
+ MI.eraseFromParent();
return true;
}
- if (CC == RISCVCC::COND_EQ || CC == RISCVCC::COND_NE)
+ if (IsEquality)
return false;
// For two constants C0 and C1 from
@@ -1432,8 +1494,6 @@ bool RISCVInstrInfo::optimizeCondBranch(MachineInstr &MI) const {
//
// To make sure this optimization is really beneficial, we only
// optimize for cases where Y had only one use (i.e. only used by the branch).
- MachineOperand &LHS = MI.getOperand(0);
- MachineOperand &RHS = MI.getOperand(1);
// Try to find the register for constant Z; return
// invalid register otherwise.
auto searchConst = [&](int64_t C1) -> Register {
@@ -1449,23 +1509,25 @@ bool RISCVInstrInfo::optimizeCondBranch(MachineInstr &MI) const {
return Register();
};
+ unsigned NewOpc = RISCVCC::getBrCond(getOppositeBranchCondition(CC));
+
// Might be case 1.
// Don't change 0 to 1 since we can use x0.
// For unsigned cases changing -1U to 0 would be incorrect.
// The incorrect case for signed would be INT_MAX, but isFromLoadImm can't
// return that.
if (isFromLoadImm(MRI, LHS, C0) && C0 != 0 && LHS.getReg().isVirtual() &&
- MRI.hasOneUse(LHS.getReg()) &&
- (CC == RISCVCC::COND_GE || CC == RISCVCC::COND_LT || C0 != -1)) {
+ MRI.hasOneUse(LHS.getReg()) && (IsSigned || C0 != -1)) {
assert(isInt<12>(C0) && "Unexpected immediate");
if (Register RegZ = searchConst(C0 + 1)) {
- reverseBranchCondition(Cond);
- Cond[1] = MachineOperand::CreateReg(RHS.getReg(), /*isDef=*/false);
- Cond[2] = MachineOperand::CreateReg(RegZ, /*isDef=*/false);
+ BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
+ .add(RHS)
+ .addReg(RegZ)
+ .addMBB(TBB);
// We might extend the live range of Z, clear its kill flag to
// account for this.
MRI.clearKillFlags(RegZ);
- modifyBranch();
+ MI.eraseFromParent();
return true;
}
}
@@ -1479,13 +1541,14 @@ bool RISCVInstrInfo::optimizeCondBranch(MachineInstr &MI) const {
MRI.hasOneUse(RHS.getReg())) {
assert(isInt<12>(C0) && "Unexpected immediate");
if (Register RegZ = searchConst(C0 - 1)) {
- reverseBranchCondition(Cond);
- Cond[1] = MachineOperand::CreateReg(RegZ, /*isDef=*/false);
- Cond[2] = MachineOperand::CreateReg(LHS.getReg(), /*isDef=*/false);
+ BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
+ .addReg(RegZ)
+ .add(LHS)
+ .addMBB(TBB);
// We might extend the live range of Z, clear its kill flag to
// account for this.
MRI.clearKillFlags(RegZ);
- modifyBranch();
+ MI.eraseFromParent();
return true;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 020be91e90e0b..785c8352d4a5e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -41,25 +41,11 @@ enum CondCode {
COND_GE,
COND_LTU,
COND_GEU,
- COND_CV_BEQIMM,
- COND_CV_BNEIMM,
- COND_QC_BEQI,
- COND_QC_BNEI,
- COND_QC_BLTI,
- COND_QC_BGEI,
- COND_QC_BLTUI,
- COND_QC_BGEUI,
- COND_QC_E_BEQI,
- COND_QC_E_BNEI,
- COND_QC_E_BLTI,
- COND_QC_E_BGEI,
- COND_QC_E_BLTUI,
- COND_QC_E_BGEUI,
COND_INVALID
};
CondCode getOppositeBranchCondition(CondCode);
-unsigned getBrCond(CondCode CC);
+unsigned getBrCond(CondCode CC, unsigned SelectOpc = 0);
} // end of namespace RISCVCC
@@ -79,7 +65,6 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
explicit RISCVInstrInfo(RISCVSubtarget &STI);
MCInst getNop() const override;
- const MCInstrDesc &getBrCond(RISCVCC::CondCode CC) const;
Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
@@ -325,9 +310,11 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
#define GET_INSTRINFO_HELPER_DECLS
#include "RISCVGenInstrInfo.inc"
+ static RISCVCC::CondCode getCondFromBranchOpc(unsigned Opc);
+
/// Return the result of the evaluation of C0 CC C1, where CC is a
/// RISCVCC::CondCode.
- static bool evaluateCondBranch(unsigned CC, int64_t C0, int64_t C1);
+ static bool evaluateCondBranch(RISCVCC::CondCode CC, int64_t C0, int64_t C1);
/// Return true if the operand is a load immediate instruction and
/// sets Imm to the immediate value.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index 942dde4bab31d..996e08bd0a27d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -789,13 +789,6 @@ let Predicates = [HasVendorXCValu, IsRV32], AddedComplexity = 1 in {
// Patterns for immediate branching operations
//===----------------------------------------------------------------------===//
-def IntCCtoRISCVCCCV : SDNodeXForm<riscv_selectcc, [{
- ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
- assert(CC == ISD::SETEQ || CC == ISD::SETNE);
- RISCVCC::CondCode BrCC = CC == ISD::SETEQ ? RISCVCC::COND_CV_BEQIMM : RISCVCC::COND_CV_BNEIMM;
- return CurDAG->getTargetConstant(BrCC, SDLoc(N), Subtarget->getXLenVT());
-}]>;
-
let Predicates = [HasVendorXCVbi, IsRV32], AddedComplexity = 2 in {
def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETEQ, bb:$imm12),
(CV_BEQIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0_bb:$imm12)>;
@@ -808,7 +801,7 @@ let Predicates = [HasVendorXCVbi, IsRV32], AddedComplexity = 2 in {
: Pat<(riscv_selectcc_frag:$cc (i32 GPR:$lhs), simm5:$Constant, Cond,
(i32 GPR:$truev), GPR:$falsev),
(Select_GPR_Using_CC_SImm5_CV GPR:$lhs, simm5:$Constant,
- (IntCCto...
[truncated]
|
lenary
approved these changes
Jun 25, 2025
wangpc-pp
approved these changes
Jun 26, 2025
This wasn't scalable and made the RISCVCC enum effectively just a different way to spelling the branch opcodes.a This patch reduces RISCVCC back down to 6 enum values. The primary user is select pseudoinstructions which now share the same encoding across all vendor extensions. The select opcode and condition code are used to determine the branch opcode when expanding the pseudo. The Cond SmallVector returned by analyzeBranch now returns the opcode instead of the RISCVCC. reverseBranchCondition now works directly on opcodes. getOppositeBranchCondition is also retained.
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…lvm#145762) This wasn't scalable and made the RISCVCC enum effectively just a different way of spelling the branch opcodes. This patch reduces RISCVCC back down to 6 enum values. The primary user is select pseudoinstructions which now share the same encoding across all vendor extensions. The select opcode and condition code are used to determine the branch opcode when expanding the pseudo. The Cond SmallVector returned by analyzeBranch now returns the opcode instead of the RISCVCC. reverseBranchCondition now works directly on opcodes. getOppositeBranchCondition is also retained. Stacked on llvm#145622
rlavaee
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Jul 1, 2025
…lvm#145762) This wasn't scalable and made the RISCVCC enum effectively just a different way of spelling the branch opcodes. This patch reduces RISCVCC back down to 6 enum values. The primary user is select pseudoinstructions which now share the same encoding across all vendor extensions. The select opcode and condition code are used to determine the branch opcode when expanding the pseudo. The Cond SmallVector returned by analyzeBranch now returns the opcode instead of the RISCVCC. reverseBranchCondition now works directly on opcodes. getOppositeBranchCondition is also retained. Stacked on llvm#145622
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This wasn't scalable and made the RISCVCC enum effectively just
a different way of spelling the branch opcodes.
This patch reduces RISCVCC back down to 6 enum values. The primary user
is select pseudoinstructions which now share the same encoding across all
vendor extensions. The select opcode and condition code are used to
determine the branch opcode when expanding the pseudo.
The Cond SmallVector returned by analyzeBranch now returns the opcode
instead of the RISCVCC. reverseBranchCondition now works directly on
opcodes. getOppositeBranchCondition is also retained.
Stacked on #145622