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[RISCV] Remove separate immediate condition codes from RISCVCC. NFC #145762

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Merged
merged 2 commits into from
Jun 26, 2025
Merged

[RISCV] Remove separate immediate condition codes from RISCVCC. NFC #145762

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1706019
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC
topperc Jun 25, 2025
15f22f8
Merge branch 'main' into pr/condbranch-part-deux
topperc Jun 26, 2025
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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -194,7 +194,7 @@ bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
CC = RISCVCC::getOppositeBranchCondition(CC);

// Insert branch instruction.
BuildMI(MBB, MBBI, DL, TII->getBrCond(CC))
BuildMI(MBB, MBBI, DL, TII->get(RISCVCC::getBrCond(CC)))
.addReg(MI.getOperand(1).getReg())
.addReg(MI.getOperand(2).getReg())
.addMBB(MergeBB);
Expand Down
9 changes: 5 additions & 4 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -21376,7 +21376,7 @@ EmitLoweredCascadedSelect(MachineInstr &First, MachineInstr &Second,
Register FLHS = First.getOperand(1).getReg();
Register FRHS = First.getOperand(2).getReg();
// Insert appropriate branch.
BuildMI(FirstMBB, DL, TII.getBrCond(FirstCC))
BuildMI(FirstMBB, DL, TII.get(RISCVCC::getBrCond(FirstCC, First.getOpcode())))
.addReg(FLHS)
.addReg(FRHS)
.addMBB(SinkMBB);
Expand All @@ -21388,7 +21388,8 @@ EmitLoweredCascadedSelect(MachineInstr &First, MachineInstr &Second,

auto SecondCC = static_cast<RISCVCC::CondCode>(Second.getOperand(3).getImm());
// Insert appropriate branch.
BuildMI(ThisMBB, DL, TII.getBrCond(SecondCC))
BuildMI(ThisMBB, DL,
TII.get(RISCVCC::getBrCond(SecondCC, Second.getOpcode())))
.addReg(SLHS)
.addReg(SRHS)
.addMBB(SinkMBB);
Expand Down Expand Up @@ -21527,12 +21528,12 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,

// Insert appropriate branch.
if (MI.getOperand(2).isImm())
BuildMI(HeadMBB, DL, TII.getBrCond(CC))
BuildMI(HeadMBB, DL, TII.get(RISCVCC::getBrCond(CC, MI.getOpcode())))
.addReg(LHS)
.addImm(MI.getOperand(2).getImm())
.addMBB(TailMBB);
else
BuildMI(HeadMBB, DL, TII.getBrCond(CC))
BuildMI(HeadMBB, DL, TII.get(RISCVCC::getBrCond(CC, MI.getOpcode())))
.addReg(LHS)
.addReg(RHS)
.addMBB(TailMBB);
Expand Down
272 changes: 162 additions & 110 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -958,54 +958,41 @@ void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
}
}

static RISCVCC::CondCode getCondFromBranchOpc(unsigned Opc) {
RISCVCC::CondCode RISCVInstrInfo::getCondFromBranchOpc(unsigned Opc) {
switch (Opc) {
default:
return RISCVCC::COND_INVALID;
case RISCV::BEQ:
return RISCVCC::COND_EQ;
case RISCV::BNE:
return RISCVCC::COND_NE;
case RISCV::BLT:
return RISCVCC::COND_LT;
case RISCV::BGE:
return RISCVCC::COND_GE;
case RISCV::BLTU:
return RISCVCC::COND_LTU;
case RISCV::BGEU:
return RISCVCC::COND_GEU;
case RISCV::CV_BEQIMM:
return RISCVCC::COND_CV_BEQIMM;
case RISCV::CV_BNEIMM:
return RISCVCC::COND_CV_BNEIMM;
case RISCV::QC_BEQI:
return RISCVCC::COND_QC_BEQI;
case RISCV::QC_E_BEQI:
return RISCVCC::COND_QC_E_BEQI;
return RISCVCC::COND_EQ;
case RISCV::BNE:
case RISCV::QC_BNEI:
return RISCVCC::COND_QC_BNEI;
case RISCV::QC_E_BNEI:
return RISCVCC::COND_QC_E_BNEI;
case RISCV::CV_BNEIMM:
return RISCVCC::COND_NE;
case RISCV::BLT:
case RISCV::QC_BLTI:
return RISCVCC::COND_QC_BLTI;
case RISCV::QC_E_BLTI:
return RISCVCC::COND_QC_E_BLTI;
return RISCVCC::COND_LT;
case RISCV::BGE:
case RISCV::QC_BGEI:
return RISCVCC::COND_QC_BGEI;
case RISCV::QC_E_BGEI:
return RISCVCC::COND_QC_E_BGEI;
return RISCVCC::COND_GE;
case RISCV::BLTU:
case RISCV::QC_BLTUI:
return RISCVCC::COND_QC_BLTUI;
case RISCV::QC_E_BLTUI:
return RISCVCC::COND_QC_E_BLTUI;
return RISCVCC::COND_LTU;
case RISCV::BGEU:
case RISCV::QC_BGEUI:
return RISCVCC::COND_QC_BGEUI;
case RISCV::QC_E_BGEUI:
return RISCVCC::COND_QC_E_BGEUI;
return RISCVCC::COND_GEU;
}
}

bool RISCVInstrInfo::evaluateCondBranch(unsigned CC, int64_t C0, int64_t C1) {
bool RISCVInstrInfo::evaluateCondBranch(RISCVCC::CondCode CC, int64_t C0,
int64_t C1) {
switch (CC) {
default:
llvm_unreachable("Unexpected CC");
Expand Down Expand Up @@ -1033,63 +1020,92 @@ static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
assert(LastInst.getDesc().isConditionalBranch() &&
"Unknown conditional branch");
Target = LastInst.getOperand(2).getMBB();
unsigned CC = getCondFromBranchOpc(LastInst.getOpcode());
Cond.push_back(MachineOperand::CreateImm(CC));
Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
Cond.push_back(LastInst.getOperand(0));
Cond.push_back(LastInst.getOperand(1));
}

unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC) {
switch (CC) {
unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC, unsigned SelectOpc) {
switch (SelectOpc) {
default:
llvm_unreachable("Unknown condition code!");
case RISCVCC::COND_EQ:
return RISCV::BEQ;
case RISCVCC::COND_NE:
return RISCV::BNE;
case RISCVCC::COND_LT:
return RISCV::BLT;
case RISCVCC::COND_GE:
return RISCV::BGE;
case RISCVCC::COND_LTU:
return RISCV::BLTU;
case RISCVCC::COND_GEU:
return RISCV::BGEU;
case RISCVCC::COND_CV_BEQIMM:
return RISCV::CV_BEQIMM;
case RISCVCC::COND_CV_BNEIMM:
return RISCV::CV_BNEIMM;
case RISCVCC::COND_QC_BEQI:
return RISCV::QC_BEQI;
case RISCVCC::COND_QC_E_BEQI:
return RISCV::QC_E_BEQI;
case RISCVCC::COND_QC_BNEI:
return RISCV::QC_BNEI;
case RISCVCC::COND_QC_E_BNEI:
return RISCV::QC_E_BNEI;
case RISCVCC::COND_QC_BLTI:
return RISCV::QC_BLTI;
case RISCVCC::COND_QC_E_BLTI:
return RISCV::QC_E_BLTI;
case RISCVCC::COND_QC_BGEI:
return RISCV::QC_BGEI;
case RISCVCC::COND_QC_E_BGEI:
return RISCV::QC_E_BGEI;
case RISCVCC::COND_QC_BLTUI:
return RISCV::QC_BLTUI;
case RISCVCC::COND_QC_E_BLTUI:
return RISCV::QC_E_BLTUI;
case RISCVCC::COND_QC_BGEUI:
return RISCV::QC_BGEUI;
case RISCVCC::COND_QC_E_BGEUI:
return RISCV::QC_E_BGEUI;
switch (CC) {
default:
llvm_unreachable("Unexpected condition code!");
case RISCVCC::COND_EQ:
return RISCV::BEQ;
case RISCVCC::COND_NE:
return RISCV::BNE;
case RISCVCC::COND_LT:
return RISCV::BLT;
case RISCVCC::COND_GE:
return RISCV::BGE;
case RISCVCC::COND_LTU:
return RISCV::BLTU;
case RISCVCC::COND_GEU:
return RISCV::BGEU;
}
break;
case RISCV::Select_GPR_Using_CC_SImm5_CV:
switch (CC) {
default:
llvm_unreachable("Unexpected condition code!");
case RISCVCC::COND_EQ:
return RISCV::CV_BEQIMM;
case RISCVCC::COND_NE:
return RISCV::CV_BNEIMM;
}
break;
case RISCV::Select_GPRNoX0_Using_CC_SImm5NonZero_QC:
switch (CC) {
default:
llvm_unreachable("Unexpected condition code!");
case RISCVCC::COND_EQ:
return RISCV::QC_BEQI;
case RISCVCC::COND_NE:
return RISCV::QC_BNEI;
case RISCVCC::COND_LT:
return RISCV::QC_BLTI;
case RISCVCC::COND_GE:
return RISCV::QC_BGEI;
}
break;
case RISCV::Select_GPRNoX0_Using_CC_UImm5NonZero_QC:
switch (CC) {
default:
llvm_unreachable("Unexpected condition code!");
case RISCVCC::COND_LTU:
return RISCV::QC_BLTUI;
case RISCVCC::COND_GEU:
return RISCV::QC_BGEUI;
}
break;
case RISCV::Select_GPRNoX0_Using_CC_SImm16NonZero_QC:
switch (CC) {
default:
llvm_unreachable("Unexpected condition code!");
case RISCVCC::COND_EQ:
return RISCV::QC_E_BEQI;
case RISCVCC::COND_NE:
return RISCV::QC_E_BNEI;
case RISCVCC::COND_LT:
return RISCV::QC_E_BLTI;
case RISCVCC::COND_GE:
return RISCV::QC_E_BGEI;
}
break;
case RISCV::Select_GPRNoX0_Using_CC_UImm16NonZero_QC:
switch (CC) {
default:
llvm_unreachable("Unexpected condition code!");
case RISCVCC::COND_LTU:
return RISCV::QC_E_BLTUI;
case RISCVCC::COND_GEU:
return RISCV::QC_E_BGEUI;
}
break;
}
}

const MCInstrDesc &RISCVInstrInfo::getBrCond(RISCVCC::CondCode CC) const {
return get(RISCVCC::getBrCond(CC));
}

RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) {
switch (CC) {
default:
Expand All @@ -1106,34 +1122,6 @@ RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) {
return RISCVCC::COND_GEU;
case RISCVCC::COND_GEU:
return RISCVCC::COND_LTU;
case RISCVCC::COND_CV_BEQIMM:
return RISCVCC::COND_CV_BNEIMM;
case RISCVCC::COND_CV_BNEIMM:
return RISCVCC::COND_CV_BEQIMM;
case RISCVCC::COND_QC_BEQI:
return RISCVCC::COND_QC_BNEI;
case RISCVCC::COND_QC_E_BEQI:
return RISCVCC::COND_QC_E_BNEI;
case RISCVCC::COND_QC_BNEI:
return RISCVCC::COND_QC_BEQI;
case RISCVCC::COND_QC_E_BNEI:
return RISCVCC::COND_QC_E_BEQI;
case RISCVCC::COND_QC_BLTI:
return RISCVCC::COND_QC_BGEI;
case RISCVCC::COND_QC_E_BLTI:
return RISCVCC::COND_QC_E_BGEI;
case RISCVCC::COND_QC_BGEI:
return RISCVCC::COND_QC_BLTI;
case RISCVCC::COND_QC_E_BGEI:
return RISCVCC::COND_QC_E_BLTI;
case RISCVCC::COND_QC_BLTUI:
return RISCVCC::COND_QC_BGEUI;
case RISCVCC::COND_QC_E_BLTUI:
return RISCVCC::COND_QC_E_BGEUI;
case RISCVCC::COND_QC_BGEUI:
return RISCVCC::COND_QC_BLTUI;
case RISCVCC::COND_QC_E_BGEUI:
return RISCVCC::COND_QC_E_BLTUI;
}
}

Expand Down Expand Up @@ -1263,9 +1251,10 @@ unsigned RISCVInstrInfo::insertBranch(
}

// Either a one or two-way conditional branch.
auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm());
MachineInstr &CondMI =
*BuildMI(&MBB, DL, getBrCond(CC)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
MachineInstr &CondMI = *BuildMI(&MBB, DL, get(Cond[0].getImm()))
.add(Cond[1])
.add(Cond[2])
.addMBB(TBB);
if (BytesAdded)
*BytesAdded += getInstSizeInBytes(CondMI);

Expand Down Expand Up @@ -1348,8 +1337,71 @@ void RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
bool RISCVInstrInfo::reverseBranchCondition(
SmallVectorImpl<MachineOperand> &Cond) const {
assert((Cond.size() == 3) && "Invalid branch condition!");
auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm());
Cond[0].setImm(getOppositeBranchCondition(CC));
switch (Cond[0].getImm()) {
default:
llvm_unreachable("Unknown conditional branch!");
case RISCV::BEQ:
Cond[0].setImm(RISCV::BNE);
break;
case RISCV::BNE:
Cond[0].setImm(RISCV::BEQ);
break;
case RISCV::BLT:
Cond[0].setImm(RISCV::BGE);
break;
case RISCV::BGE:
Cond[0].setImm(RISCV::BLT);
break;
case RISCV::BLTU:
Cond[0].setImm(RISCV::BGEU);
break;
case RISCV::BGEU:
Cond[0].setImm(RISCV::BLTU);
break;
case RISCV::CV_BEQIMM:
Cond[0].setImm(RISCV::CV_BNEIMM);
break;
case RISCV::CV_BNEIMM:
Cond[0].setImm(RISCV::CV_BEQIMM);
break;
case RISCV::QC_BEQI:
Cond[0].setImm(RISCV::QC_BNEI);
break;
case RISCV::QC_BNEI:
Cond[0].setImm(RISCV::QC_BEQI);
break;
case RISCV::QC_BGEI:
Cond[0].setImm(RISCV::QC_BLTI);
break;
case RISCV::QC_BLTI:
Cond[0].setImm(RISCV::QC_BGEI);
break;
case RISCV::QC_BGEUI:
Cond[0].setImm(RISCV::QC_BLTUI);
break;
case RISCV::QC_BLTUI:
Cond[0].setImm(RISCV::QC_BGEUI);
break;
case RISCV::QC_E_BEQI:
Cond[0].setImm(RISCV::QC_E_BNEI);
break;
case RISCV::QC_E_BNEI:
Cond[0].setImm(RISCV::QC_E_BEQI);
break;
case RISCV::QC_E_BGEI:
Cond[0].setImm(RISCV::QC_E_BLTI);
break;
case RISCV::QC_E_BLTI:
Cond[0].setImm(RISCV::QC_E_BGEI);
break;
case RISCV::QC_E_BGEUI:
Cond[0].setImm(RISCV::QC_E_BLTUI);
break;
case RISCV::QC_E_BLTUI:
Cond[0].setImm(RISCV::QC_E_BGEUI);
break;
}

return false;
}

Expand Down
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