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[test] -march -> -mtriple (#67741)
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‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: | FileCheck -check-prefix=RV32I %s
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---

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: | FileCheck -check-prefix=RV64I %s
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---

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv32 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: | FileCheck -check-prefix=RV32I %s
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---

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv64 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: | FileCheck -check-prefix=RV64I %s
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---

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy32.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: | FileCheck -check-prefix=RV32I %s
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---

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy64.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: | FileCheck -check-prefix=RV64I %s
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---

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: | FileCheck -check-prefix=RV32I %s
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---

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv64.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: | FileCheck -check-prefix=RV64I %s
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---

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv32 -mattr=+m -run-pass=regbankselect \
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# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck -check-prefix=RV32I %s
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‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv64 -mattr=+m -run-pass=regbankselect \
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# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck -check-prefix=RV64I %s
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‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv32 -run-pass=regbankselect \
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# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck -check-prefix=RV32I %s
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‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv64 -run-pass=regbankselect \
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# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck -check-prefix=RV64I %s
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‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv64 -run-pass=regbankselect \
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# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck -check-prefix=RV64I %s
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‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv32 -run-pass=regbankselect \
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# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck -check-prefix=RV32I %s
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‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv64 -run-pass=regbankselect \
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# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck -check-prefix=RV64I %s
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‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv32 -run-pass=regbankselect \
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# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck -check-prefix=RV32I %s
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‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv64 -run-pass=regbankselect \
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# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck -check-prefix=RV64I %s
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‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv32 -run-pass=regbankselect \
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# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck -check-prefix=RV32I %s
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‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv64 -run-pass=regbankselect \
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# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck -check-prefix=RV64I %s
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‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv32 -run-pass=regbankselect \
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# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck -check-prefix=RV32I %s
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‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv64 -run-pass=regbankselect \
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# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck -check-prefix=RV64I %s
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‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv32 -run-pass=regbankselect \
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# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck -check-prefix=RV32I %s
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‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv64 -run-pass=regbankselect \
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# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck -check-prefix=RV64I %s
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‎llvm/test/CodeGen/RISCV/copy-frameindex.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv64 -debugify-and-strip-all-safe -run-pass machine-sink %s -o - 2>&1 | FileCheck %s
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# RUN: llc -mtriple=riscv64 -debugify-and-strip-all-safe -run-pass machine-sink %s -o - 2>&1 | FileCheck %s
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--- |
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define void @sink_addi_fi(i32 %0) !dbg !5 {

‎llvm/test/CodeGen/RISCV/live-sp.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv64 -run-pass=prologepilog -simplify-mir -o - %s | FileCheck %s
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# RUN: llc -mtriple=riscv64 -run-pass=prologepilog -simplify-mir -o - %s | FileCheck %s
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# verify live-on-entry registers are not marked killed by spills
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--- |
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‎llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir

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# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=OUTLINED,RV32I-MO %s
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# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=OUTLINED,RV64I-MO %s
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# CFIs are invisible (they can be outlined, but won't actually impact the outlining result) if there

‎llvm/test/CodeGen/RISCV/machine-outliner-position.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=RV32I-MO %s
4-
# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=RV64I-MO %s
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# Position instructions are illegal to outline. The first instruction won't be outlined

‎llvm/test/CodeGen/RISCV/machineoutliner-jumptable.mir

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# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefix=RV32I-MO %s
3-
# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefix=RV64I-MO %s
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--- |

‎llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck %s
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# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck %s
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# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir --function-sections -verify-machineinstrs < %s \
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# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir --function-sections -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefix=CHECK-FS %s
8-
# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir --function-sections -verify-machineinstrs < %s \
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# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir --function-sections -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefix=CHECK-FS %s
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--- |

‎llvm/test/CodeGen/RISCV/machineoutliner.mir

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# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=CHECK,RV32I-MO %s
3-
# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=CHECK,RV64I-MO %s
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--- |

‎llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -march=riscv64 -mattr=+v -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s
2+
# RUN: llc -mtriple=riscv64 -mattr=+v -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s
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--- |
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define void @add_scalable_offset(

‎llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv64 -mattr=+v -run-pass=register-coalescer %s -o - 2>&1 | FileCheck %s
2+
# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=register-coalescer %s -o - 2>&1 | FileCheck %s
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# This test used to crash in the register coalescer when the target would
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# return the out-of-bounds CommuteAnyOperandIndex for one of its commutable

‎llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv64 -mattr=+v -o - %s \
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# RUN: llc -mtriple=riscv64 -mattr=+v -o - %s \
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# RUN: -stop-after=prologepilog | FileCheck %s
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--- |

‎llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -march=riscv64 -mattr=+v -verify-machineinstrs \
2+
# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
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# RUN: -start-after finalize-isel -stop-after prologepilog -o - %s | FileCheck %s
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--- |

‎llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -march=riscv64 -mattr=+v -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s
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# RUN: llc -mtriple=riscv64 -mattr=+v -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"

‎llvm/test/CodeGen/RISCV/stack-inst-compress.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
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# RUN: llc -march=riscv32 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \
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# RUN: llc -mtriple=riscv32 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=CHECK-RV32-NO-COM %s
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# RUN: llc -march=riscv32 -mattr=+c -x mir -run-pass=prologepilog \
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# RUN: llc -mtriple=riscv32 -mattr=+c -x mir -run-pass=prologepilog \
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# RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK-RV32-COM %s
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# RUN: llc -march=riscv64 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \
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# RUN: llc -mtriple=riscv64 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=CHECK-RV64-NO-COM %s
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# RUN: llc -march=riscv64 -mattr=+c -x mir -run-pass=prologepilog \
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# RUN: llc -mtriple=riscv64 -mattr=+c -x mir -run-pass=prologepilog \
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# RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK-RV64-COM %s
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--- |
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define dso_local void @_Z15stack_size_2048v() {

‎llvm/test/CodeGen/RISCV/stack-slot-coloring.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv32 -run-pass=greedy,virtregrewriter,stack-slot-coloring %s -o - 2>&1 | FileCheck %s
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# RUN: llc -mtriple=riscv32 -run-pass=greedy,virtregrewriter,stack-slot-coloring %s -o - 2>&1 | FileCheck %s
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--- |
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define dso_local i32 @main() local_unnamed_addr {

‎llvm/test/CodeGen/RISCV/verify-instr.mir

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# RUN: not --crash llc -march=riscv32 -run-pass machineverifier %s -o - 2>&1 | FileCheck %s
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# RUN: not --crash llc -mtriple=riscv32 -run-pass machineverifier %s -o - 2>&1 | FileCheck %s
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# CHECK: *** Bad machine code: Invalid immediate ***
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# CHECK: - instruction: $x2 = ADDI $x1, 10000

‎llvm/test/MachineVerifier/test_g_brindirect_is_indirect_branch.mir

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# RUN: llc -march=riscv32 -o - -run-pass=none -verify-machineinstrs %s | FileCheck %s
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# RUN: llc -mtriple=riscv32 -o - -run-pass=none -verify-machineinstrs %s | FileCheck %s
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# REQUIRES: riscv-registered-target
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# This test checks that the G_BRINDIRECT is an indirect branch by leveraging

‎llvm/test/MachineVerifier/test_g_brjt_is_indirect_branch.mir

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# RUN: llc -march=riscv32 -o - -run-pass=none -verify-machineinstrs %s | FileCheck %s
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# RUN: llc -mtriple=riscv32 -o - -run-pass=none -verify-machineinstrs %s | FileCheck %s
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# REQUIRES: riscv-registered-target
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# This test checks that the G_BRJT is an indirect branch by leveraging RISCV's

‎llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -march=riscv32 -mattr=+zve32x,+zvl32b -interleaved-access -S | FileCheck %s -check-prefix=ZVL32B
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; RUN: opt < %s -mtriple=riscv32 -mattr=+zve32x,+zvl32b -interleaved-access -S | FileCheck %s -check-prefix=ZVL32B
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; RUN: opt < %s -mtriple=riscv32 -mattr=+zve32x,+zvl128b -interleaved-access -S | FileCheck %s -check-prefix=ZVL128B
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; Make sure that we don't lower interleaved loads that won't fit into the minimum vlen

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