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Merged
merged 1 commit into from
Sep 29, 2023
Merged

[test] -march -> -mtriple #67741

merged 1 commit into from
Sep 29, 2023

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francisvm
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Similar to cfc1a87

@llvmbot
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llvmbot commented Sep 28, 2023 •
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@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-llvm-transforms

Changes

Similar to cfc1a87

Patch is 28.77 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/67741.diff

41 Files Affected:

  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy32.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy64.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv64.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/copy-frameindex.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/live-sp.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/machine-outliner-position.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/machineoutliner-jumptable.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir (+4-4)
  • (modified) llvm/test/CodeGen/RISCV/machineoutliner.mir (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/stack-inst-compress.mir (+4-4)
  • (modified) llvm/test/CodeGen/RISCV/stack-slot-coloring.mir (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/verify-instr.mir (+1-1)
  • (modified) llvm/test/MachineVerifier/test_g_brindirect_is_indirect_branch.mir (+1-1)
  • (modified) llvm/test/MachineVerifier/test_g_brjt_is_indirect_branch.mir (+1-1)
  • (modified) llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll (+1-1)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
index c063e5a97c394ec..2ef5de501ee7116 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
 # RUN: | FileCheck -check-prefix=RV32I %s
 
 ---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
index 84cc55f422a6a0c..1c3e92d6669d6d1 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
 # RUN: | FileCheck -check-prefix=RV64I %s
 
 ---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir
index d02b0b6f0e0124d..868bc2c37778e5e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
 # RUN: | FileCheck -check-prefix=RV32I %s
 
 ---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
index 9b37c12bf3a3599..f748f0811a99c67 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
 # RUN: | FileCheck -check-prefix=RV64I %s
 
 ---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy32.mir
index 123596b2cef3583..a0ec98b145470ea 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy32.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
 # RUN: | FileCheck -check-prefix=RV32I %s
 
 ---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy64.mir
index 1251a812bba09cf..bb15aa50bb561f7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy64.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
 # RUN: | FileCheck -check-prefix=RV64I %s
 
 ---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir
index bc36cbfced584ef..459511eb94358cf 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
 # RUN: | FileCheck -check-prefix=RV32I %s
 
 ---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv64.mir
index 3f960985b617e14..8512af316f54108 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv64.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
 # RUN: | FileCheck -check-prefix=RV64I %s
 
 ---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
index 5e17407f9bfb9a0..6f8d76953de4fb7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -mattr=+m -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=regbankselect \
 # RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck -check-prefix=RV32I %s
 
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
index 6d87e3dcb4c36c2..26120f770413623 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -mattr=+m -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=regbankselect \
 # RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck -check-prefix=RV64I %s
 
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
index eac5201e4fe2537..7e02e7d25d2da9e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
 # RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck -check-prefix=RV32I %s
 
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
index 0141dbaa2edc8a0..c162ac0b6e996c3 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
 # RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck -check-prefix=RV64I %s
 
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
index 0ea1b3162e9aa0e..e6a8f4100f4e769 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
 # RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck -check-prefix=RV64I %s
 
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
index 965388a0f355bac..8cea5fd19007c9c 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
 # RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck -check-prefix=RV32I %s
 
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
index 86b5fc64abd33e8..36146c158d8a591 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
 # RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck -check-prefix=RV64I %s
 
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
index 4f0d973808b6e37..ed86fb2725c7a01 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
 # RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck -check-prefix=RV32I %s
 
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
index a1d76ec3d73fb80..64533de67d3b695 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
 # RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck -check-prefix=RV64I %s
 
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
index 80e73f93e80e6bc..b8bedfae987d31b 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
 # RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck -check-prefix=RV32I %s
 
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
index b0f86991f275668..e7db66b37bd2bfd 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
 # RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck -check-prefix=RV64I %s
 
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
index e08cebdcba2e76a..fe5c799187480d4 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
 # RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck -check-prefix=RV32I %s
 
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
index 93999fd93c8342c..df3f6319debfa5c 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
 # RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck -check-prefix=RV64I %s
 
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
index 6dc46fca6f256d0..903cc868e69e4e5 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
 # RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck -check-prefix=RV32I %s
 
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
index 1f70ecf442d0b85..3ea9a51dc4203f1 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
 # RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
 # RUN:   -o - | FileCheck -check-prefix=RV64I %s
 
diff --git a/llvm/test/CodeGen/RISCV/copy-frameindex.mir b/llvm/test/CodeGen/RISCV/copy-frameindex.mir
index 87636e0a96b40a7..f220751daad4c84 100644
--- a/llvm/test/CodeGen/RISCV/copy-frameindex.mir
+++ b/llvm/test/CodeGen/RISCV/copy-frameindex.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -debugify-and-strip-all-safe -run-pass machine-sink %s -o - 2>&1 | FileCheck %s
+# RUN: llc -mtriple=riscv64 -debugify-and-strip-all-safe -run-pass machine-sink %s -o - 2>&1 | FileCheck %s
 
 --- |
   define void @sink_addi_fi(i32 %0) !dbg !5 {
diff --git a/llvm/test/CodeGen/RISCV/live-sp.mir b/llvm/test/CodeGen/RISCV/live-sp.mir
index 2210fd1a8a927ec..5df6a79755cb460 100644
--- a/llvm/test/CodeGen/RISCV/live-sp.mir
+++ b/llvm/test/CodeGen/RISCV/live-sp.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=prologepilog -simplify-mir  -o - %s | FileCheck %s
+# RUN: llc -mtriple=riscv64 -run-pass=prologepilog -simplify-mir  -o - %s | FileCheck %s
 # verify live-on-entry registers are not marked killed by spills
 --- |
 
diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir b/llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir
index fa0ef9e76f3c7f7..6ecca6a1b18ef89 100644
--- a/llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir
+++ b/llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir
@@ -1,6 +1,6 @@
-# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
 # RUN: | FileCheck -check-prefixes=OUTLINED,RV32I-MO %s
-# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
 # RUN: | FileCheck -check-prefixes=OUTLINED,RV64I-MO %s
 
 # CFIs are invisible (they can be outlined, but won't actually impact the outlining result) if there
diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-position.mir b/llvm/test/CodeGen/RISCV/machine-outliner-position.mir
index e6c101758a937f0..715e212eecabb39 100644
--- a/llvm/test/CodeGen/RISCV/machine-outliner-position.mir
+++ b/llvm/test/CodeGen/RISCV/machine-outliner-position.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
 # RUN: | FileCheck -check-prefixes=RV32I-MO %s
-# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
 # RUN: | FileCheck -check-prefixes=RV64I-MO %s
 
 # Position instructions are illegal to outline. The first instruction won't be outlined
diff --git a/llvm/test/CodeGen/RISCV/machineoutliner-jumptable.mir b/llvm/test/CodeGen/RISCV/machineoutliner-jumptable.mir
index 885db0aa5023cdb..563d155fd5dc3ff 100644
--- a/llvm/test/CodeGen/RISCV/machineoutliner-jumptable.mir
+++ b/llvm/test/CodeGen/RISCV/machineoutliner-jumptable.mir
@@ -1,6 +1,6 @@
-# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
 # RUN: | FileCheck -check-prefix=RV32I-MO %s
-# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
 # RUN: | FileCheck -check-prefix=RV64I-MO %s
 
 --- |
diff --git a/llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir b/llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir
index 91bc20e15da78fa..34f7a93b6a168c3 100644
--- a/llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir
+++ b/llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir
@@ -1,11 +1,11 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
 # RUN: | FileCheck %s
-# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
 # RUN: | FileCheck %s
-# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir --function-sections -verify-machineinstrs < %s \
+# RUN: llc ...
[truncated]

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MaskRay commented Sep 29, 2023

Better to say that this is similar to 806761a

@francisvm francisvm merged commit cc9ba56 into llvm:main Sep 29, 2023
@francisvm francisvm deleted the march-to-mtriple branch September 29, 2023 17:43
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@MaskRay MaskRay MaskRay approved these changes

@fpetrogalli fpetrogalli fpetrogalli approved these changes

@topperc topperc Awaiting requested review from topperc

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