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[LoongArch] Override TargetFrameLowering::spillCalleeSavedRegisters
When using `llvm.returnaddress` intrinsic, special handling is required for the spill of the `RA` register. Otherwise it will cause the verifier fail in some cases (e.g. pr17377.c of the GCC C Torture Suite). Specifically: ``` *** Bad machine code: Using an undefined physical register *** - function: f - basic block: %bb.0 entry (0xd94d18) - instruction: ST_D killed $r1, $r22, -40 :: (store (s64) into %stack.2) - operand 0: killed $r1 ``` Reviewed By: SixWeining Differential Revision: https://reviews.llvm.org/D137387
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llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp

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Original file line numberDiff line numberDiff line change
@@ -406,6 +406,29 @@ LoongArchFrameLowering::eliminateCallFramePseudoInstr(
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return MBB.erase(MI);
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}
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bool LoongArchFrameLowering::spillCalleeSavedRegisters(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
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if (CSI.empty())
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return true;
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MachineFunction *MF = MBB.getParent();
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const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
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// Insert the spill to the stack frame.
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for (auto &CS : CSI) {
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Register Reg = CS.getReg();
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// If the register is RA and the return address is taken by method
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// LoongArchTargetLowering::lowerRETURNADDR, don't set kill flag.
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bool IsKill =
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!(Reg == LoongArch::R1 && MF->getFrameInfo().isReturnAddressTaken());
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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TII.storeRegToStackSlot(MBB, MI, Reg, IsKill, CS.getFrameIdx(), RC, TRI);
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}
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return true;
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}
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StackOffset LoongArchFrameLowering::getFrameIndexReference(
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const MachineFunction &MF, int FI, Register &FrameReg) const {
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const MachineFrameInfo &MFI = MF.getFrameInfo();

llvm/lib/Target/LoongArch/LoongArchFrameLowering.h

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@@ -41,6 +41,10 @@ class LoongArchFrameLowering : public TargetFrameLowering {
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MachineBasicBlock::iterator
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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ArrayRef<CalleeSavedInfo> CSI,
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const TargetRegisterInfo *TRI) const override;
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StackOffset getFrameIndexReference(const MachineFunction &MF, int FI,
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Register &FrameReg) const override;
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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,102 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s
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;; This test case is reduced from pr17377.c of the GCC C Torture Suite using
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;; bugpoint.
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@calls = external dso_local global i32, align 4
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declare ptr @llvm.returnaddress(i32 immarg)
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define dso_local ptr @f(i32 noundef signext %i) "frame-pointer"="all" {
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; CHECK-LABEL: f:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi.d $sp, $sp, -48
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: st.d $ra, $sp, 40 # 8-byte Folded Spill
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; CHECK-NEXT: st.d $fp, $sp, 32 # 8-byte Folded Spill
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; CHECK-NEXT: .cfi_offset 1, -8
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; CHECK-NEXT: .cfi_offset 22, -16
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; CHECK-NEXT: addi.d $fp, $sp, 48
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; CHECK-NEXT: .cfi_def_cfa 22, 0
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; CHECK-NEXT: st.d $ra, $fp, -40 # 8-byte Folded Spill
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; CHECK-NEXT: move $a1, $a0
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(calls)
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; CHECK-NEXT: addi.d $a3, $a0, %pc_lo12(calls)
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; CHECK-NEXT: ld.wu $a0, $a3, 0
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; CHECK-NEXT: addi.d $a2, $a0, 1
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; CHECK-NEXT: st.w $a2, $a3, 0
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; CHECK-NEXT: st.w $a1, $fp, -28
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; CHECK-NEXT: bnez $a0, .LBB0_2
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; CHECK-NEXT: b .LBB0_1
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; CHECK-NEXT: .LBB0_1: # %if.then
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; CHECK-NEXT: ld.d $a0, $fp, -40 # 8-byte Folded Reload
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; CHECK-NEXT: st.d $a0, $fp, -24
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; CHECK-NEXT: b .LBB0_7
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; CHECK-NEXT: .LBB0_2: # %if.end
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; CHECK-NEXT: ld.wu $a0, $fp, -28
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; CHECK-NEXT: st.d $a0, $fp, -48 # 8-byte Folded Spill
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; CHECK-NEXT: beqz $a0, .LBB0_5
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; CHECK-NEXT: b .LBB0_3
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; CHECK-NEXT: .LBB0_3: # %if.end
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; CHECK-NEXT: ld.d $a0, $fp, -48 # 8-byte Folded Reload
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; CHECK-NEXT: ori $a1, $zero, 1
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; CHECK-NEXT: bne $a0, $a1, .LBB0_6
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; CHECK-NEXT: b .LBB0_4
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; CHECK-NEXT: .LBB0_4: # %sw.bb
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(f)
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; CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(f)
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; CHECK-NEXT: st.d $a0, $fp, -24
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; CHECK-NEXT: b .LBB0_7
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; CHECK-NEXT: .LBB0_5: # %sw.bb1
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; CHECK-NEXT: ld.d $a0, $fp, -40 # 8-byte Folded Reload
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; CHECK-NEXT: st.d $a0, $fp, -24
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; CHECK-NEXT: b .LBB0_7
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; CHECK-NEXT: .LBB0_6: # %sw.epilog
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; CHECK-NEXT: move $a0, $zero
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; CHECK-NEXT: st.d $a0, $fp, -24
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; CHECK-NEXT: b .LBB0_7
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; CHECK-NEXT: .LBB0_7: # %return
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; CHECK-NEXT: ld.d $a0, $fp, -24
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; CHECK-NEXT: ld.d $fp, $sp, 32 # 8-byte Folded Reload
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; CHECK-NEXT: ld.d $ra, $sp, 40 # 8-byte Folded Reload
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; CHECK-NEXT: addi.d $sp, $sp, 48
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; CHECK-NEXT: ret
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entry:
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%retval = alloca ptr, align 8
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%i.addr = alloca i32, align 4
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store i32 %i, ptr %i.addr, align 4
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%0 = load i32, ptr @calls, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, ptr @calls, align 4
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%cmp = icmp eq i32 %0, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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%1 = call ptr @llvm.returnaddress(i32 0)
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store ptr %1, ptr %retval, align 8
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br label %return
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if.end:
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%2 = load i32, ptr %i.addr, align 4
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switch i32 %2, label %sw.epilog [
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i32 1, label %sw.bb
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i32 0, label %sw.bb1
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]
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sw.bb:
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store ptr @f, ptr %retval, align 8
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br label %return
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sw.bb1:
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%3 = call ptr @llvm.returnaddress(i32 0)
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store ptr %3, ptr %retval, align 8
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br label %return
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sw.epilog:
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store ptr null, ptr %retval, align 8
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br label %return
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return:
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%4 = load ptr, ptr %retval, align 8
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ret ptr %4
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}

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