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michaelmaitlandwangpc-pp
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[RISCV] Split PseudoVFMUL by SEW
Co-authored-by: Wang Pengcheng <[email protected]>
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-24
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‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2832,16 +2832,17 @@ multiclass VPseudoVDIV_VV_VX {
28322832

28332833
multiclass VPseudoVFMUL_VV_VF_RM {
28342834
foreach m = MxListF in {
2835-
defm "" : VPseudoBinaryFV_VV_RM<m>,
2836-
SchedBinary<"WriteVFMulV", "ReadVFMulV", "ReadVFMulV", m.MX,
2837-
forceMergeOpRead=true>;
2835+
foreach e = SchedSEWSet<m.MX, isF=1>.val in
2836+
defm "" : VPseudoBinaryFV_VV_RM<m, "", sew=e>,
2837+
SchedBinary<"WriteVFMulV", "ReadVFMulV", "ReadVFMulV", m.MX, e,
2838+
forceMergeOpRead=true>;
28382839
}
28392840

28402841
foreach f = FPList in {
28412842
foreach m = f.MxList in {
2842-
defm "" : VPseudoBinaryV_VF_RM<m, f>,
2843+
defm "" : VPseudoBinaryV_VF_RM<m, f, "", sew=f.SEW>,
28432844
SchedBinary<"WriteVFMulF", "ReadVFMulV", "ReadVFMulF", m.MX,
2844-
forceMergeOpRead=true>;
2845+
f.SEW, forceMergeOpRead=true>;
28452846
}
28462847
}
28472848
}
@@ -7106,7 +7107,7 @@ defm : VPatBinaryW_WV_WX_RM<"int_riscv_vfwsub_w", "PseudoVFWSUB",
71067107
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
71077108
//===----------------------------------------------------------------------===//
71087109
defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfmul", "PseudoVFMUL",
7109-
AllFloatVectors>;
7110+
AllFloatVectors, isSEWAware=1>;
71107111
defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfdiv", "PseudoVFDIV",
71117112
AllFloatVectors, isSEWAware=1>;
71127113
defm : VPatBinaryV_VX_RM<"int_riscv_vfrdiv", "PseudoVFRDIV",

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1213,7 +1213,7 @@ defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF_RM<fadd, "PseudoVFWADD">;
12131213
defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF_RM<fsub, "PseudoVFWSUB">;
12141214

12151215
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
1216-
defm : VPatBinaryFPSDNode_VV_VF_RM<any_fmul, "PseudoVFMUL">;
1216+
defm : VPatBinaryFPSDNode_VV_VF_RM<any_fmul, "PseudoVFMUL", isSEWAware=1>;
12171217
defm : VPatBinaryFPSDNode_VV_VF_RM<any_fdiv, "PseudoVFDIV", isSEWAware=1>;
12181218
defm : VPatBinaryFPSDNode_R_VF_RM<any_fdiv, "PseudoVFRDIV", isSEWAware=1>;
12191219

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2443,7 +2443,7 @@ defm : VPatBinaryFPWVL_VV_VF_WV_WF_RM<riscv_vfwsub_vl, riscv_vfwsub_w_vl,
24432443
"PseudoVFWSUB", isSEWAware=1>;
24442444

24452445
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
2446-
defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fmul_vl, "PseudoVFMUL">;
2446+
defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fmul_vl, "PseudoVFMUL", isSEWAware=1>;
24472447
defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fdiv_vl, "PseudoVFDIV", isSEWAware=1>;
24482448
defm : VPatBinaryFPVL_R_VF_RM<any_riscv_fdiv_vl, "PseudoVFRDIV", isSEWAware=1>;
24492449

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -739,15 +739,15 @@ foreach mx = SchedMxListF in {
739739
let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
740740
defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
741741
defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
742+
defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
743+
defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
742744
}
743745
}
744746
}
745747
foreach mx = SchedMxList in {
746748
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
747749
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
748750
let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
749-
defm "" : LMULWriteResMX<"WriteVFMulV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
750-
defm "" : LMULWriteResMX<"WriteVFMulF", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
751751
defm "" : LMULWriteResMX<"WriteVFMulAddV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
752752
defm "" : LMULWriteResMX<"WriteVFMulAddF", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
753753
defm "" : LMULWriteResMX<"WriteVFRecpV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
@@ -1157,8 +1157,8 @@ defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;
11571157
defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;
11581158
defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>;
11591159
defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>;
1160-
defm "" : LMULReadAdvance<"ReadVFMulV", 0>;
1161-
defm "" : LMULReadAdvance<"ReadVFMulF", 0>;
1160+
defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>;
1161+
defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>;
11621162
defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;
11631163
defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;
11641164
defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>;

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -493,15 +493,16 @@ foreach mx = SchedMxListF in {
493493
let Latency = 6, ReleaseAtCycles = [LMulLat] in {
494494
defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
495495
defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
496+
defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
497+
defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
498+
496499
}
497500
}
498501
}
499502
foreach mx = SchedMxList in {
500503
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
501504
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
502505
let Latency = 6, ReleaseAtCycles = [LMulLat] in {
503-
defm "" : LMULWriteResMX<"WriteVFMulV", [SiFiveP600VectorArith], mx, IsWorstCase>;
504-
defm "" : LMULWriteResMX<"WriteVFMulF", [SiFiveP600VectorArith], mx, IsWorstCase>;
505506
defm "" : LMULWriteResMX<"WriteVFMulAddV", [SiFiveP600VectorArith], mx, IsWorstCase>;
506507
defm "" : LMULWriteResMX<"WriteVFMulAddF", [SiFiveP600VectorArith], mx, IsWorstCase>;
507508
}
@@ -945,8 +946,8 @@ defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;
945946
defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;
946947
defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>;
947948
defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>;
948-
defm "" : LMULReadAdvance<"ReadVFMulV", 0>;
949-
defm "" : LMULReadAdvance<"ReadVFMulF", 0>;
949+
defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>;
950+
defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>;
950951
defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;
951952
defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;
952953
defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>;

‎llvm/lib/Target/RISCV/RISCVScheduleV.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -415,8 +415,8 @@ defm "" : LMULSEWSchedWritesF<"WriteVFALUF">;
415415
defm "" : LMULSEWSchedWritesFW<"WriteVFWALUV">;
416416
defm "" : LMULSEWSchedWritesFW<"WriteVFWALUF">;
417417
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
418-
defm "" : LMULSchedWrites<"WriteVFMulV">;
419-
defm "" : LMULSchedWrites<"WriteVFMulF">;
418+
defm "" : LMULSEWSchedWritesF<"WriteVFMulV">;
419+
defm "" : LMULSEWSchedWritesF<"WriteVFMulF">;
420420
defm "" : LMULSEWSchedWritesF<"WriteVFDivV">;
421421
defm "" : LMULSEWSchedWritesF<"WriteVFDivF">;
422422
// 13.5. Vector Widening Floating-Point Multiply
@@ -640,8 +640,8 @@ defm "" : LMULSEWSchedReadsF<"ReadVFALUF">;
640640
defm "" : LMULSEWSchedReadsFW<"ReadVFWALUV">;
641641
defm "" : LMULSEWSchedReadsFW<"ReadVFWALUF">;
642642
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
643-
defm "" : LMULSchedReads<"ReadVFMulV">;
644-
defm "" : LMULSchedReads<"ReadVFMulF">;
643+
defm "" : LMULSEWSchedReadsF<"ReadVFMulV">;
644+
defm "" : LMULSEWSchedReadsF<"ReadVFMulF">;
645645
defm "" : LMULSEWSchedReadsF<"ReadVFDivV">;
646646
defm "" : LMULSEWSchedReadsF<"ReadVFDivF">;
647647
// 13.5. Vector Widening Floating-Point Multiply
@@ -884,8 +884,8 @@ defm "" : LMULSEWWriteResF<"WriteVFALUV", []>;
884884
defm "" : LMULSEWWriteResF<"WriteVFALUF", []>;
885885
defm "" : LMULSEWWriteResFW<"WriteVFWALUV", []>;
886886
defm "" : LMULSEWWriteResFW<"WriteVFWALUF", []>;
887-
defm "" : LMULWriteRes<"WriteVFMulV", []>;
888-
defm "" : LMULWriteRes<"WriteVFMulF", []>;
887+
defm "" : LMULSEWWriteResF<"WriteVFMulV", []>;
888+
defm "" : LMULSEWWriteResF<"WriteVFMulF", []>;
889889
defm "" : LMULSEWWriteResF<"WriteVFDivV", []>;
890890
defm "" : LMULSEWWriteResF<"WriteVFDivF", []>;
891891
defm "" : LMULSEWWriteResFW<"WriteVFWMulV", []>;
@@ -1040,8 +1040,8 @@ defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;
10401040
defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;
10411041
defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>;
10421042
defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>;
1043-
defm "" : LMULReadAdvance<"ReadVFMulV", 0>;
1044-
defm "" : LMULReadAdvance<"ReadVFMulF", 0>;
1043+
defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>;
1044+
defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>;
10451045
defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;
10461046
defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;
10471047
defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>;

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