Skip to content

Commit d6ec3aa

Browse files
author
Kai Luo
committed
Do not skip
1 parent 57b6171 commit d6ec3aa

11 files changed

+75
-82
lines changed

‎llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -642,17 +642,10 @@ bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
642642
(RegClass->hasSuperClassEq(&PPC::CRRCRegClass) ||
643643
RegClass->hasSuperClassEq(&PPC::CRBITRCRegClass))) {
644644
std::set<MCPhysReg> ModifiedRegisters;
645-
bool Skip = true;
646-
// Scan from the last instruction writes VirtReg to the beginning of the
647-
// MBB.
648645
for (MachineInstr &MI :
649646
llvm::make_range(LastUseMBB->rbegin(), LastUseMBB->rend())) {
650647
if (MI.isDebugInstr())
651648
continue;
652-
if (MI.modifiesRegister(VirtReg, TRI))
653-
Skip = false;
654-
if (Skip)
655-
continue;
656649
for (MachineOperand &MO : MI.operands()) {
657650
if (!MO.isReg() || !MO.getReg() || !MO.getReg().isVirtual() ||
658651
!MO.isDef() || !VRM->hasPhys(MO.getReg()))

‎llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-maxmin.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -10,8 +10,8 @@ define ppc_fp128 @test_maxfe(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128
1010
; CHECK: # %bb.0: # %entry
1111
; CHECK-NEXT: fcmpu 0, 6, 4
1212
; CHECK-NEXT: fcmpu 1, 5, 3
13-
; CHECK-NEXT: crand 20, 6, 1
14-
; CHECK-NEXT: cror 20, 5, 20
13+
; CHECK-NEXT: crand 24, 6, 1
14+
; CHECK-NEXT: cror 20, 5, 24
1515
; CHECK-NEXT: bc 12, 20, .LBB0_2
1616
; CHECK-NEXT: # %bb.1: # %entry
1717
; CHECK-NEXT: fmr 6, 4
@@ -22,8 +22,8 @@ define ppc_fp128 @test_maxfe(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128
2222
; CHECK-NEXT: fmr 5, 3
2323
; CHECK-NEXT: .LBB0_4: # %entry
2424
; CHECK-NEXT: fcmpu 1, 5, 1
25-
; CHECK-NEXT: crand 20, 6, 1
26-
; CHECK-NEXT: cror 20, 5, 20
25+
; CHECK-NEXT: crand 24, 6, 1
26+
; CHECK-NEXT: cror 20, 5, 24
2727
; CHECK-NEXT: bc 12, 20, .LBB0_6
2828
; CHECK-NEXT: # %bb.5: # %entry
2929
; CHECK-NEXT: fmr 6, 2
@@ -34,8 +34,8 @@ define ppc_fp128 @test_maxfe(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128
3434
; CHECK-NEXT: fmr 5, 1
3535
; CHECK-NEXT: .LBB0_8: # %entry
3636
; CHECK-NEXT: fcmpu 1, 5, 7
37-
; CHECK-NEXT: crand 20, 6, 1
38-
; CHECK-NEXT: cror 20, 5, 20
37+
; CHECK-NEXT: crand 24, 6, 1
38+
; CHECK-NEXT: cror 20, 5, 24
3939
; CHECK-NEXT: bc 12, 20, .LBB0_10
4040
; CHECK-NEXT: # %bb.9: # %entry
4141
; CHECK-NEXT: fmr 5, 7
@@ -136,8 +136,8 @@ define ppc_fp128 @test_minfe(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128
136136
; CHECK: # %bb.0: # %entry
137137
; CHECK-NEXT: fcmpu 0, 6, 4
138138
; CHECK-NEXT: fcmpu 1, 5, 3
139-
; CHECK-NEXT: crand 20, 6, 0
140-
; CHECK-NEXT: cror 20, 4, 20
139+
; CHECK-NEXT: crand 24, 6, 0
140+
; CHECK-NEXT: cror 20, 4, 24
141141
; CHECK-NEXT: bc 12, 20, .LBB3_2
142142
; CHECK-NEXT: # %bb.1: # %entry
143143
; CHECK-NEXT: fmr 6, 4
@@ -148,8 +148,8 @@ define ppc_fp128 @test_minfe(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128
148148
; CHECK-NEXT: fmr 5, 3
149149
; CHECK-NEXT: .LBB3_4: # %entry
150150
; CHECK-NEXT: fcmpu 1, 5, 1
151-
; CHECK-NEXT: crand 20, 6, 0
152-
; CHECK-NEXT: cror 20, 4, 20
151+
; CHECK-NEXT: crand 24, 6, 0
152+
; CHECK-NEXT: cror 20, 4, 24
153153
; CHECK-NEXT: bc 12, 20, .LBB3_6
154154
; CHECK-NEXT: # %bb.5: # %entry
155155
; CHECK-NEXT: fmr 6, 2
@@ -160,8 +160,8 @@ define ppc_fp128 @test_minfe(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128
160160
; CHECK-NEXT: fmr 5, 1
161161
; CHECK-NEXT: .LBB3_8: # %entry
162162
; CHECK-NEXT: fcmpu 1, 5, 7
163-
; CHECK-NEXT: crand 20, 6, 0
164-
; CHECK-NEXT: cror 20, 4, 20
163+
; CHECK-NEXT: crand 24, 6, 0
164+
; CHECK-NEXT: cror 20, 4, 24
165165
; CHECK-NEXT: bc 12, 20, .LBB3_10
166166
; CHECK-NEXT: # %bb.9: # %entry
167167
; CHECK-NEXT: fmr 5, 7

‎llvm/test/CodeGen/PowerPC/common-chain-aix32.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -38,10 +38,10 @@ define i64 @two_chain_same_offset_succ_i32(ptr %p, i32 %offset, i32 %base1, i64
3838
; CHECK-LABEL: two_chain_same_offset_succ_i32:
3939
; CHECK: # %bb.0: # %entry
4040
; CHECK-NEXT: cmplwi r6, 0
41-
; CHECK-NEXT: cmpwi cr1, r6, 0
42-
; CHECK-NEXT: crandc 4*cr5+lt, 4*cr1+lt, eq
41+
; CHECK-NEXT: cmpwi cr5, r6, 0
4342
; CHECK-NEXT: cmpwi cr1, r7, 0
44-
; CHECK-NEXT: bc 12, 4*cr5+lt, L..BB0_6
43+
; CHECK-NEXT: crandc 4*cr6+lt, 4*cr5+lt, eq
44+
; CHECK-NEXT: bc 12, 4*cr6+lt, L..BB0_6
4545
; CHECK-NEXT: # %bb.1: # %entry
4646
; CHECK-NEXT: crand 4*cr5+lt, eq, 4*cr1+eq
4747
; CHECK-NEXT: bc 12, 4*cr5+lt, L..BB0_6
@@ -74,11 +74,11 @@ define i64 @two_chain_same_offset_succ_i32(ptr %p, i32 %offset, i32 %base1, i64
7474
; CHECK-NEXT: addze r3, r3
7575
; CHECK-NEXT: addic r11, r11, 1
7676
; CHECK-NEXT: addze r10, r10
77-
; CHECK-NEXT: cmplw r10, r6
78-
; CHECK-NEXT: cmpw cr1, r10, r6
79-
; CHECK-NEXT: crandc 4*cr5+lt, 4*cr1+lt, eq
8077
; CHECK-NEXT: cmplw cr1, r11, r7
81-
; CHECK-NEXT: bc 12, 4*cr5+lt, L..BB0_3
78+
; CHECK-NEXT: cmplw r10, r6
79+
; CHECK-NEXT: cmpw cr5, r10, r6
80+
; CHECK-NEXT: crandc 4*cr6+lt, 4*cr5+lt, eq
81+
; CHECK-NEXT: bc 12, 4*cr6+lt, L..BB0_3
8282
; CHECK-NEXT: # %bb.4: # %for.body
8383
; CHECK-NEXT: #
8484
; CHECK-NEXT: crand 4*cr5+lt, eq, 4*cr1+lt

‎llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -70,15 +70,15 @@ define float @fooul(float %X) #0 {
7070
; PPC64-NEXT: lfs 0, .LCPI2_0@toc@l(3)
7171
; PPC64-NEXT: rldic 4, 4, 63, 0
7272
; PPC64-NEXT: fsubs 2, 1, 0
73-
; PPC64-NEXT: fcmpu 0, 1, 0
73+
; PPC64-NEXT: fcmpu 1, 1, 0
7474
; PPC64-NEXT: fctidz 2, 2
7575
; PPC64-NEXT: stfd 2, -8(1)
7676
; PPC64-NEXT: fctidz 2, 1
7777
; PPC64-NEXT: stfd 2, -16(1)
7878
; PPC64-NEXT: ld 3, -8(1)
7979
; PPC64-NEXT: ld 5, -16(1)
8080
; PPC64-NEXT: xor 3, 3, 4
81-
; PPC64-NEXT: bc 12, 0, .LBB2_1
81+
; PPC64-NEXT: bc 12, 4, .LBB2_1
8282
; PPC64-NEXT: b .LBB2_2
8383
; PPC64-NEXT: .LBB2_1: # %entry
8484
; PPC64-NEXT: addi 3, 5, 0
@@ -106,15 +106,15 @@ define float @fooul(float %X) #0 {
106106
; PPC64-NEXT: rldicl 5, 5, 53, 11
107107
; PPC64-NEXT: std 4, -32(1)
108108
; PPC64-NEXT: rldicl 4, 5, 11, 1
109-
; PPC64-NEXT: cmpldi 1, 7, 1
110-
; PPC64-NEXT: bc 12, 5, .LBB2_6
109+
; PPC64-NEXT: cmpldi 5, 7, 1
110+
; PPC64-NEXT: bc 12, 21, .LBB2_6
111111
; PPC64-NEXT: # %bb.5: # %entry
112112
; PPC64-NEXT: ori 4, 6, 0
113113
; PPC64-NEXT: b .LBB2_6
114114
; PPC64-NEXT: .LBB2_6: # %entry
115-
; PPC64-NEXT: cmpdi 5, 3, 0
115+
; PPC64-NEXT: cmpdi 6, 3, 0
116116
; PPC64-NEXT: std 4, -24(1)
117-
; PPC64-NEXT: bc 12, 20, .LBB2_8
117+
; PPC64-NEXT: bc 12, 24, .LBB2_8
118118
; PPC64-NEXT: # %bb.7: # %entry
119119
; PPC64-NEXT: lfd 0, -32(1)
120120
; PPC64-NEXT: fcfid 0, 0

‎llvm/test/CodeGen/PowerPC/is_fpclass.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -420,15 +420,15 @@ define i1 @isclass_00d_double(double %x) nounwind {
420420
; CHECK-LABEL: isclass_00d_double:
421421
; CHECK: # %bb.0:
422422
; CHECK-NEXT: mffprd 3, 1
423-
; CHECK-NEXT: xststdcdp 0, 1, 127
424-
; CHECK-NEXT: xststdcdp 1, 1, 64
425-
; CHECK-NEXT: xststdcdp 7, 1, 16
423+
; CHECK-NEXT: xststdcdp 1, 1, 127
424+
; CHECK-NEXT: xststdcdp 6, 1, 64
426425
; CHECK-NEXT: rldicl 3, 3, 32, 32
427-
; CHECK-NEXT: crandc 20, 0, 2
426+
; CHECK-NEXT: crandc 20, 4, 6
428427
; CHECK-NEXT: andis. 3, 3, 8
429428
; CHECK-NEXT: li 3, 1
430-
; CHECK-NEXT: crand 24, 6, 2
431-
; CHECK-NEXT: cror 21, 30, 24
429+
; CHECK-NEXT: crand 28, 26, 2
430+
; CHECK-NEXT: xststdcdp 0, 1, 16
431+
; CHECK-NEXT: cror 21, 2, 28
432432
; CHECK-NEXT: crnor 20, 21, 20
433433
; CHECK-NEXT: isel 3, 0, 3, 20
434434
; CHECK-NEXT: blr

‎llvm/test/CodeGen/PowerPC/ppc-rotate-clear.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -53,11 +53,11 @@ declare i32 @llvm.fshl.i32(i32, i32, i32) #0
5353
define dso_local i64 @rotatemask64(i64 noundef %word) local_unnamed_addr #0 {
5454
; AIX32-LABEL: rotatemask64:
5555
; AIX32: # %bb.0: # %entry
56-
; AIX32-NEXT: cmplwi r3, 0
56+
; AIX32-NEXT: cmplwi cr1, r3, 0
5757
; AIX32-NEXT: cntlzw r6, r4
5858
; AIX32-NEXT: addi r6, r6, 32
5959
; AIX32-NEXT: cntlzw r5, r3
60-
; AIX32-NEXT: iseleq r5, r6, r5
60+
; AIX32-NEXT: isel r5, r6, r5, 4*cr1+eq
6161
; AIX32-NEXT: andi. r6, r5, 32
6262
; AIX32-NEXT: clrlwi r5, r5, 27
6363
; AIX32-NEXT: iseleq r6, r3, r4
@@ -101,11 +101,11 @@ declare i64 @llvm.fshl.i64(i64, i64, i64) #1
101101
define dso_local i64 @rotatemask64_2(i64 noundef %word) local_unnamed_addr #0 {
102102
; AIX32-LABEL: rotatemask64_2:
103103
; AIX32: # %bb.0: # %entry
104-
; AIX32-NEXT: cmplwi r3, 0
104+
; AIX32-NEXT: cmplwi cr1, r3, 0
105105
; AIX32-NEXT: cntlzw r6, r4
106106
; AIX32-NEXT: addi r6, r6, 32
107107
; AIX32-NEXT: cntlzw r5, r3
108-
; AIX32-NEXT: iseleq r5, r6, r5
108+
; AIX32-NEXT: isel r5, r6, r5, 4*cr1+eq
109109
; AIX32-NEXT: andi. r6, r5, 32
110110
; AIX32-NEXT: clrlwi r5, r5, 27
111111
; AIX32-NEXT: iseleq r6, r3, r4
@@ -147,11 +147,11 @@ entry:
147147
define dso_local i64 @rotatemask64_3(i64 noundef %word) local_unnamed_addr #0 {
148148
; AIX32-LABEL: rotatemask64_3:
149149
; AIX32: # %bb.0: # %entry
150-
; AIX32-NEXT: cmplwi r3, 0
150+
; AIX32-NEXT: cmplwi cr1, r3, 0
151151
; AIX32-NEXT: cntlzw r6, r4
152152
; AIX32-NEXT: addi r6, r6, 32
153153
; AIX32-NEXT: cntlzw r5, r3
154-
; AIX32-NEXT: iseleq r5, r6, r5
154+
; AIX32-NEXT: isel r5, r6, r5, 4*cr1+eq
155155
; AIX32-NEXT: andi. r6, r5, 32
156156
; AIX32-NEXT: clrlwi r5, r5, 27
157157
; AIX32-NEXT: iseleq r6, r3, r4
@@ -307,12 +307,12 @@ define dso_local i64 @twomasks(i64 noundef %word) local_unnamed_addr #0 {
307307
; AIX32: # %bb.0: # %entry
308308
; AIX32-NEXT: mflr r0
309309
; AIX32-NEXT: stwu r1, -64(r1)
310-
; AIX32-NEXT: cmplwi r3, 0
310+
; AIX32-NEXT: cmplwi cr1, r3, 0
311311
; AIX32-NEXT: cntlzw r6, r4
312312
; AIX32-NEXT: stw r0, 72(r1)
313313
; AIX32-NEXT: addi r6, r6, 32
314314
; AIX32-NEXT: cntlzw r5, r3
315-
; AIX32-NEXT: iseleq r5, r6, r5
315+
; AIX32-NEXT: isel r5, r6, r5, 4*cr1+eq
316316
; AIX32-NEXT: andi. r6, r5, 32
317317
; AIX32-NEXT: clrlwi r5, r5, 27
318318
; AIX32-NEXT: iseleq r6, r3, r4
@@ -397,12 +397,12 @@ define dso_local i64 @tworotates(i64 noundef %word) local_unnamed_addr #0 {
397397
; AIX32: # %bb.0: # %entry
398398
; AIX32-NEXT: mflr r0
399399
; AIX32-NEXT: stwu r1, -64(r1)
400-
; AIX32-NEXT: cmplwi r3, 0
400+
; AIX32-NEXT: cmplwi cr1, r3, 0
401401
; AIX32-NEXT: cntlzw r6, r4
402402
; AIX32-NEXT: stw r0, 72(r1)
403403
; AIX32-NEXT: addi r6, r6, 32
404404
; AIX32-NEXT: cntlzw r5, r3
405-
; AIX32-NEXT: iseleq r5, r6, r5
405+
; AIX32-NEXT: isel r5, r6, r5, 4*cr1+eq
406406
; AIX32-NEXT: andi. r6, r5, 32
407407
; AIX32-NEXT: clrlwi r5, r5, 27
408408
; AIX32-NEXT: iseleq r6, r3, r4

‎llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1373,33 +1373,33 @@ define void @setbn4(i128 %0, ptr %sel.out) {
13731373
; CHECK-LABEL: setbn4:
13741374
; CHECK: # %bb.0: # %entry
13751375
; CHECK-NEXT: li r6, 1
1376-
; CHECK-NEXT: cmpdi cr1, r3, 0
1376+
; CHECK-NEXT: cmpdi cr6, r3, 0
13771377
; CHECK-NEXT: li r3, 1
13781378
; CHECK-NEXT: rldic r6, r6, 48, 15
1379-
; CHECK-NEXT: cmpld r4, r6
1380-
; CHECK-NEXT: crandc 4*cr5+lt, gt, eq
1381-
; CHECK-NEXT: crandc 4*cr6+lt, eq, 4*cr1+eq
1382-
; CHECK-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
1379+
; CHECK-NEXT: cmpld cr1, r4, r6
13831380
; CHECK-NEXT: rldicl. r4, r4, 16, 48
13841381
; CHECK-NEXT: li r4, -1
1385-
; CHECK-NEXT: isel r3, 0, r3, 4*cr7+lt
1382+
; CHECK-NEXT: crandc 4*cr5+lt, 4*cr1+gt, 4*cr1+eq
1383+
; CHECK-NEXT: crandc 4*cr7+lt, 4*cr1+eq, 4*cr6+eq
1384+
; CHECK-NEXT: crnor 4*cr5+lt, 4*cr7+lt, 4*cr5+lt
1385+
; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt
13861386
; CHECK-NEXT: iseleq r3, r4, r3
13871387
; CHECK-NEXT: stw r3, 0(r5)
13881388
; CHECK-NEXT: blr
13891389
;
13901390
; CHECK-PWR8-LABEL: setbn4:
13911391
; CHECK-PWR8: # %bb.0: # %entry
13921392
; CHECK-PWR8-NEXT: li r6, 1
1393-
; CHECK-PWR8-NEXT: cmpdi cr1, r3, 0
1393+
; CHECK-PWR8-NEXT: cmpdi cr6, r3, 0
13941394
; CHECK-PWR8-NEXT: li r3, 1
13951395
; CHECK-PWR8-NEXT: rldic r6, r6, 48, 15
1396-
; CHECK-PWR8-NEXT: cmpld r4, r6
1397-
; CHECK-PWR8-NEXT: crandc 4*cr5+lt, gt, eq
1398-
; CHECK-PWR8-NEXT: crandc 4*cr6+lt, eq, 4*cr1+eq
1396+
; CHECK-PWR8-NEXT: cmpld cr1, r4, r6
13991397
; CHECK-PWR8-NEXT: rldicl. r4, r4, 16, 48
14001398
; CHECK-PWR8-NEXT: li r4, -1
1401-
; CHECK-PWR8-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
1402-
; CHECK-PWR8-NEXT: isel r3, 0, r3, 4*cr7+lt
1399+
; CHECK-PWR8-NEXT: crandc 4*cr5+lt, 4*cr1+gt, 4*cr1+eq
1400+
; CHECK-PWR8-NEXT: crandc 4*cr7+lt, 4*cr1+eq, 4*cr6+eq
1401+
; CHECK-PWR8-NEXT: crnor 4*cr5+lt, 4*cr7+lt, 4*cr5+lt
1402+
; CHECK-PWR8-NEXT: isel r3, 0, r3, 4*cr5+lt
14031403
; CHECK-PWR8-NEXT: iseleq r3, r4, r3
14041404
; CHECK-PWR8-NEXT: stw r3, 0(r5)
14051405
; CHECK-PWR8-NEXT: blr

‎llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1628,11 +1628,11 @@ define ppc_fp128 @testppc_fp128eq(ppc_fp128 %c1, ppc_fp128 %c2, ppc_fp128 %c3, p
16281628
; CHECK: # %bb.0: # %entry
16291629
; CHECK-NEXT: fcmpu 0, 6, 8
16301630
; CHECK-NEXT: fcmpu 1, 5, 7
1631-
; CHECK-NEXT: crand 20, 6, 2
1632-
; CHECK-NEXT: fcmpu 6, 2, 4
1633-
; CHECK-NEXT: fcmpu 7, 1, 3
1634-
; CHECK-NEXT: crand 21, 30, 26
1635-
; CHECK-NEXT: crxor 20, 21, 20
1631+
; CHECK-NEXT: crand 24, 6, 2
1632+
; CHECK-NEXT: fcmpu 7, 2, 4
1633+
; CHECK-NEXT: fcmpu 0, 1, 3
1634+
; CHECK-NEXT: crand 20, 2, 30
1635+
; CHECK-NEXT: crxor 20, 20, 24
16361636
; CHECK-NEXT: bc 12, 20, .LBB50_2
16371637
; CHECK-NEXT: # %bb.1: # %entry
16381638
; CHECK-NEXT: fmr 11, 9
@@ -1649,11 +1649,11 @@ define ppc_fp128 @testppc_fp128eq(ppc_fp128 %c1, ppc_fp128 %c2, ppc_fp128 %c3, p
16491649
; CHECK-NO-ISEL: # %bb.0: # %entry
16501650
; CHECK-NO-ISEL-NEXT: fcmpu 0, 6, 8
16511651
; CHECK-NO-ISEL-NEXT: fcmpu 1, 5, 7
1652-
; CHECK-NO-ISEL-NEXT: crand 20, 6, 2
1653-
; CHECK-NO-ISEL-NEXT: fcmpu 6, 2, 4
1654-
; CHECK-NO-ISEL-NEXT: fcmpu 7, 1, 3
1655-
; CHECK-NO-ISEL-NEXT: crand 21, 30, 26
1656-
; CHECK-NO-ISEL-NEXT: crxor 20, 21, 20
1652+
; CHECK-NO-ISEL-NEXT: crand 24, 6, 2
1653+
; CHECK-NO-ISEL-NEXT: fcmpu 7, 2, 4
1654+
; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 3
1655+
; CHECK-NO-ISEL-NEXT: crand 20, 2, 30
1656+
; CHECK-NO-ISEL-NEXT: crxor 20, 20, 24
16571657
; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB50_2
16581658
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
16591659
; CHECK-NO-ISEL-NEXT: fmr 11, 9

‎llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -241,14 +241,14 @@ define i1 @test_urem_oversized(i66 %X) nounwind {
241241
; PPC-NEXT: add 4, 4, 7
242242
; PPC-NEXT: add 3, 4, 3
243243
; PPC-NEXT: rlwimi 10, 3, 31, 0, 0
244-
; PPC-NEXT: cmplw 5, 11
245-
; PPC-NEXT: cmplwi 1, 10, 13
244+
; PPC-NEXT: cmplw 1, 5, 11
245+
; PPC-NEXT: cmplwi 5, 10, 13
246246
; PPC-NEXT: rlwinm 3, 3, 31, 31, 31
247-
; PPC-NEXT: crand 20, 6, 0
248-
; PPC-NEXT: crandc 24, 4, 6
247+
; PPC-NEXT: crand 24, 22, 4
248+
; PPC-NEXT: crandc 28, 20, 22
249249
; PPC-NEXT: rlwimi. 3, 6, 1, 30, 30
250-
; PPC-NEXT: cror 28, 20, 24
251-
; PPC-NEXT: crnand 20, 2, 28
250+
; PPC-NEXT: cror 20, 24, 28
251+
; PPC-NEXT: crnand 20, 2, 20
252252
; PPC-NEXT: li 3, 1
253253
; PPC-NEXT: bc 12, 20, .LBB5_1
254254
; PPC-NEXT: blr

‎llvm/test/CodeGen/PowerPC/vec-min-max.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -245,12 +245,12 @@ define i128 @invalidv1i128(<2 x i128> %v1, <2 x i128> %v2) {
245245
; CHECK-NEXT: cmpld 4, 3
246246
; CHECK-NEXT: xxswapd 0, 36
247247
; CHECK-NEXT: xxswapd 1, 34
248-
; CHECK-NEXT: cmpd 1, 4, 3
248+
; CHECK-NEXT: cmpd 5, 4, 3
249249
; CHECK-NEXT: mffprd 3, 0
250250
; CHECK-NEXT: mffprd 4, 1
251-
; CHECK-NEXT: crandc 20, 4, 2
252251
; CHECK-NEXT: cmpld 1, 4, 3
253-
; CHECK-NEXT: bc 12, 20, .LBB12_3
252+
; CHECK-NEXT: crandc 24, 20, 2
253+
; CHECK-NEXT: bc 12, 24, .LBB12_3
254254
; CHECK-NEXT: # %bb.1:
255255
; CHECK-NEXT: crand 20, 2, 4
256256
; CHECK-NEXT: bc 12, 20, .LBB12_3

‎llvm/test/CodeGen/PowerPC/vsx_builtins.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -139,10 +139,10 @@ declare i32 @llvm.ppc.vsx.xvtsqrtsp(<4 x float>)
139139
define i32 @xvtdivdp_andi(<2 x double> %a, <2 x double> %b) {
140140
; CHECK-LABEL: xvtdivdp_andi:
141141
; CHECK: # %bb.0: # %entry
142-
; CHECK-NEXT: xvtdivdp cr0, v2, v3
142+
; CHECK-NEXT: xvtdivdp cr1, v2, v3
143143
; CHECK-NEXT: li r4, 222
144-
; CHECK-NEXT: mfocrf r3, 128
145-
; CHECK-NEXT: srwi r3, r3, 28
144+
; CHECK-NEXT: mfocrf r3, 64
145+
; CHECK-NEXT: rlwinm r3, r3, 8, 28, 31
146146
; CHECK-NEXT: andi. r3, r3, 2
147147
; CHECK-NEXT: li r3, 22
148148
; CHECK-NEXT: iseleq r3, r4, r3

0 commit comments

Comments
 (0)