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[AArch64] Add assembly/disassembly for BFMOP4{A,S} (non-widening) instructions
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‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

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@@ -1034,3 +1034,8 @@ let Predicates = [HasSME2, HasSVEBFSCALE] in {
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defm BFMUL : sme2_bfmul_single<"bfmul">;
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defm BFMUL : sme2_bfmul_multi<"bfmul">;
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} //[HasSME2, HasSVEBFSCALE]
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let Predicates = [HasSME2p2, HasSMEB16B16] in {
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defm BFMOP4A : sme2_bfmop4as_non_widening<0, "bfmop4a">;
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defm BFMOP4S : sme2_bfmop4as_non_widening<1, "bfmop4s">;
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}

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

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@@ -6262,6 +6262,8 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
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case Match_InvalidMatrixTileVectorV128:
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return Error(Loc,
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"invalid matrix operand, expected za[0-15]h.q or za[0-15]v.q");
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case Match_InvalidMatrixTile16:
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return Error(Loc, "invalid matrix operand, expected za[0-1].h");
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case Match_InvalidMatrixTile32:
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return Error(Loc, "invalid matrix operand, expected za[0-3].s");
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case Match_InvalidMatrixTile64:
@@ -6882,6 +6884,7 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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case Match_InvalidSVEExactFPImmOperandHalfOne:
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case Match_InvalidSVEExactFPImmOperandHalfTwo:
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case Match_InvalidSVEExactFPImmOperandZeroOne:
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case Match_InvalidMatrixTile16:
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case Match_InvalidMatrixTile32:
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case Match_InvalidMatrixTile64:
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case Match_InvalidMatrix:

‎llvm/lib/Target/AArch64/SMEInstrFormats.td

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@@ -5335,3 +5335,40 @@ multiclass sme2_bfmul_multi<string mnemonic> {
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def _2Z2Z : sme2_multi2_fmul_mm<0b00, mnemonic, ZZ_h_mul_r>;
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def _4Z4Z : sme2_multi4_fmul_mm<0b00, mnemonic, ZZZZ_h_mul_r>;
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}
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class sme2_bf16_fp16_quarter_tile_outer_product<bit M, bit N, bit S, string mnemonic, RegisterOperand zn_ty, RegisterOperand zm_ty>
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: I<(outs TileOp16:$ZAda),
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(ins TileOp16:$_ZAda, zn_ty:$Zn, zm_ty:$Zm),
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mnemonic, "\t$ZAda, $Zn, $Zm",
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"", []>, Sched<[]> {
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bit ZAda;
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bits<3> Zn;
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bits<3> Zm;
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let Inst{31-21} = 0b10000001001;
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let Inst{20} = M;
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let Inst{19-17} = Zm;
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let Inst{16-10} = 0b0000000;
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let Inst{9} = N;
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let Inst{8-6} = Zn;
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let Inst{5} = 0;
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let Inst{4} = S;
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let Inst{3-1} = 0b100;
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let Inst{0} = ZAda;
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let Constraints = "$ZAda = $_ZAda";
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}
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multiclass sme2_bfmop4as_non_widening<bit S, string mnemonic> {
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// Single vectors
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def _ZZ_H : sme2_bf16_fp16_quarter_tile_outer_product<0, 0, S, mnemonic, ZPR16Mul2_Lo, ZPR16Mul2_Hi>;
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// Multiple and single vectors
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def _2ZZ_H : sme2_bf16_fp16_quarter_tile_outer_product<0, 1, S, mnemonic, ZZ_h_mul_r_Lo, ZPR16Mul2_Hi>;
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// Single and multiple vectors
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def _Z2Z_H : sme2_bf16_fp16_quarter_tile_outer_product<1, 0, S, mnemonic, ZPR16Mul2_Lo, ZZ_h_mul_r_Hi>;
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// Multiple vectors
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def _2Z2Z_H : sme2_bf16_fp16_quarter_tile_outer_product<1, 1, S, mnemonic, ZZ_h_mul_r_Lo, ZZ_h_mul_r_Hi>;
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}

‎llvm/test/MC/AArch64/SME2p2/bfmop4as-non-widening-diagnostics.s

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@@ -0,0 +1,220 @@
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// RUN: not llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-b16b16 < %s 2>&1 | FileCheck %s
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// BFMOP4A
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// Single vectors
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bfmop4a za0.d, z0.h, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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bfmop4a za4.h, z0.h, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmop4a za0.h, z0.s, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h
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bfmop4a za0.h, z15.h, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h
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bfmop4a za0.h, z16.h, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h
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bfmop4a za0.h, z0.h, z16.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h
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bfmop4a za0.h, z12.h, z17.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h
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bfmop4a za0.h, z12.h, z14.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h
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bfmop4a za0.h, z12.h, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h
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// Single and multiple vectors
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bfmop4a za0.d, z0.h, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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bfmop4a za4.h, z0.h, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmop4a za0.h, z0.s, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h
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bfmop4a za0.h, z1.h, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h
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bfmop4a za0.h, z16.h, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h
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bfmop4a za0.h, z0.h, {z16.s-z17.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmop4a za0.h, z0.h, {z17.h-z18.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types
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bfmop4a za0.h, z0.h, {z12.h-z13.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types
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// Multiple and single vectors
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bfmop4a za0.d, {z0.h-z1.h}, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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bfmop4a za4.h, {z0.h-z1.h}, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmop4a za0.h, {z0.s-z1.h}, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
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bfmop4a za0.h, {z1.h-z2.h}, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types
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bfmop4a za0.h, {z16.h-z17.h}, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types
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bfmop4a za0.h, {z0.h-z1.h}, z16.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h
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bfmop4a za0.h, {z0.h-z1.h}, z17.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h
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bfmop4a za0.h, {z0.h-z1.h}, z12.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h
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// Multiple vectors
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bfmop4a za0.d, {z0.h-z1.h}, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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bfmop4a za4.h, {z0.h-z1.h}, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmop4a za0.h, {z0.s-z1.s}, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmop4a za0.h, {z1.h-z2.h}, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types
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bfmop4a za0.h, {z18.h-z19.h}, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types
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bfmop4a za0.h, {z0.h-z1.h}, {z16.s-z17.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmop4a za0.h, {z0.h-z1.h}, {z19.h-z20.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types
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bfmop4a za0.h, {z0.h-z1.h}, {z10.h-z11.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types
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// BFMOP4S
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// Single vectors
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bfmop4s za0.d, z0.h, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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bfmop4s za4.h, z0.h, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmop4s za0.h, z0.s, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h
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bfmop4s za0.h, z15.h, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h
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bfmop4s za0.h, z16.h, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h
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bfmop4s za0.h, z0.h, z16.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h
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bfmop4s za0.h, z12.h, z17.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h
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bfmop4s za0.h, z12.h, z14.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h
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bfmop4s za0.h, z12.h, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h
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// Single and multiple vectors
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bfmop4s za0.d, z0.h, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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bfmop4s za4.h, z0.h, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmop4s za0.h, z0.s, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h
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bfmop4s za0.h, z1.h, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h
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bfmop4s za0.h, z16.h, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h
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bfmop4s za0.h, z0.h, {z16.s-z17.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmop4s za0.h, z0.h, {z17.h-z18.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types
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bfmop4s za0.h, z0.h, {z12.h-z13.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types
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// Multiple and single vectors
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bfmop4s za0.d, {z0.h-z1.h}, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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bfmop4s za4.h, {z0.h-z1.h}, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmop4s za0.h, {z0.s-z1.h}, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
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bfmop4s za0.h, {z1.h-z2.h}, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types
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bfmop4s za0.h, {z16.h-z17.h}, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types
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bfmop4s za0.h, {z0.h-z1.h}, z16.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h
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bfmop4s za0.h, {z0.h-z1.h}, z17.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h
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bfmop4s za0.h, {z0.h-z1.h}, z12.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h
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// Multiple vectors
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bfmop4s za0.d, {z0.h-z1.h}, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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bfmop4s za4.h, {z0.h-z1.h}, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmop4s za0.h, {z0.s-z1.s}, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmop4s za0.h, {z1.h-z2.h}, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types
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bfmop4s za0.h, {z18.h-z19.h}, {z16.h-z17.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types
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bfmop4s za0.h, {z0.h-z1.h}, {z16.s-z17.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmop4s za0.h, {z0.h-z1.h}, {z19.h-z20.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types
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bfmop4s za0.h, {z0.h-z1.h}, {z10.h-z11.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types

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