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[CodeGen] Use llvm::append_range (NFC) (#133603)
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9 files changed

+10
-21
lines changed

9 files changed

+10
-21
lines changed

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1477,8 +1477,7 @@ static uint64_t getOffsetFromIndices(const User &U, const DataLayout &DL) {
14771477
for (auto Idx : IVI->indices())
14781478
Indices.push_back(ConstantInt::get(Int32Ty, Idx));
14791479
} else {
1480-
for (Value *Op : drop_begin(U.operands()))
1481-
Indices.push_back(Op);
1480+
llvm::append_range(Indices, drop_begin(U.operands()));
14821481
}
14831482

14841483
return 8 * static_cast<uint64_t>(
@@ -2212,8 +2211,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
22122211
case Intrinsic::fake_use: {
22132212
SmallVector<llvm::SrcOp, 4> VRegs;
22142213
for (const auto &Arg : CI.args())
2215-
for (auto VReg : getOrCreateVRegs(*Arg))
2216-
VRegs.push_back(VReg);
2214+
llvm::append_range(VRegs, getOrCreateVRegs(*Arg));
22172215
MIRBuilder.buildInstr(TargetOpcode::FAKE_USE, {}, VRegs);
22182216
MF->setHasFakeUses(true);
22192217
return true;

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4906,8 +4906,7 @@ LegalizerHelper::fewerElementsVectorMultiEltType(
49064906
SmallVector<Register, 8> SplitPieces;
49074907
extractVectorParts(MI.getReg(UseIdx), NumElts, SplitPieces, MIRBuilder,
49084908
MRI);
4909-
for (auto Reg : SplitPieces)
4910-
InputOpsPieces[UseNo].push_back(Reg);
4909+
llvm::append_range(InputOpsPieces[UseNo], SplitPieces);
49114910
}
49124911
}
49134912

llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4218,9 +4218,7 @@ std::optional<ValueIDNum> InstrRefBasedLDV::resolveDbgPHIsImpl(
42184218
}
42194219

42204220
// Sort PHIs to validate into RPO-order.
4221-
SmallVector<LDVSSAPhi *, 8> SortedPHIs;
4222-
for (auto &PHI : CreatedPHIs)
4223-
SortedPHIs.push_back(PHI);
4221+
SmallVector<LDVSSAPhi *, 8> SortedPHIs(CreatedPHIs);
42244222

42254223
llvm::sort(SortedPHIs, [&](LDVSSAPhi *A, LDVSSAPhi *B) {
42264224
return BBToOrder[&A->getParent()->BB] < BBToOrder[&B->getParent()->BB];

llvm/lib/CodeGen/MachineSink.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2326,8 +2326,7 @@ bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
23262326
for (MCRegUnit Unit : TRI->regunits(MO.getReg())) {
23272327
for (const auto &MIRegs : SeenDbgInstrs.lookup(Unit)) {
23282328
auto &Regs = DbgValsToSinkMap[MIRegs.first];
2329-
for (Register Reg : MIRegs.second)
2330-
Regs.push_back(Reg);
2329+
llvm::append_range(Regs, MIRegs.second);
23312330
}
23322331
}
23332332
}

llvm/lib/CodeGen/RegAllocGreedy.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2195,8 +2195,7 @@ MCRegister RAGreedy::tryLastChanceRecoloring(
21952195
if (tryRecoloringCandidates(RecoloringQueue, CurrentNewVRegs,
21962196
FixedRegisters, RecolorStack, Depth)) {
21972197
// Push the queued vregs into the main queue.
2198-
for (Register NewVReg : CurrentNewVRegs)
2199-
NewVRegs.push_back(NewVReg);
2198+
llvm::append_range(NewVRegs, CurrentNewVRegs);
22002199
// Do not mess up with the global assignment process.
22012200
// I.e., VirtReg must be unassigned.
22022201
if (VRM->hasPhys(ThisVirtReg)) {

llvm/lib/CodeGen/SelectOptimize.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -451,8 +451,7 @@ void SelectOptimizeImpl::optimizeSelectsInnerLoops(Function &F,
451451
SmallVector<Loop *, 4> Loops(LI->begin(), LI->end());
452452
// Need to check size on each iteration as we accumulate child loops.
453453
for (unsigned long i = 0; i < Loops.size(); ++i)
454-
for (Loop *ChildL : Loops[i]->getSubLoops())
455-
Loops.push_back(ChildL);
454+
llvm::append_range(Loops, Loops[i]->getSubLoops());
456455

457456
for (Loop *L : Loops) {
458457
if (!L->isInnermost())

llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1195,8 +1195,7 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
11951195
// Add rounding control registers as implicit def for function call.
11961196
if (II.isCall() && MF->getFunction().hasFnAttribute(Attribute::StrictFP)) {
11971197
ArrayRef<MCPhysReg> RCRegs = TLI->getRoundingControlRegisters();
1198-
for (MCPhysReg Reg : RCRegs)
1199-
UsedRegs.push_back(Reg);
1198+
llvm::append_range(UsedRegs, RCRegs);
12001199
}
12011200

12021201
// Finally mark unused registers as dead.

llvm/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -197,8 +197,7 @@ class SDDbgValue {
197197
for (const SDDbgOperand &DbgOp : getLocationOps())
198198
if (DbgOp.getKind() == SDDbgOperand::SDNODE)
199199
Dependencies.push_back(DbgOp.getSDNode());
200-
for (SDNode *Node : getAdditionalDependencies())
201-
Dependencies.push_back(Node);
200+
llvm::append_range(Dependencies, getAdditionalDependencies());
202201
return Dependencies;
203202
}
204203

llvm/lib/CodeGen/WindowScheduler.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -283,8 +283,7 @@ void WindowScheduler::restoreMBB() {
283283
MI.eraseFromParent();
284284
}
285285
// Restore MBB to the state before window scheduling.
286-
for (auto *MI : OriMIs)
287-
MBB->push_back(MI);
286+
llvm::append_range(*MBB, OriMIs);
288287
updateLiveIntervals();
289288
}
290289

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