[CodeGen] Use llvm::append_range (NFC) #133603
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llvmbot
added
debuginfo
llvm:globalisel
llvm:SelectionDAG
|
@llvm/pr-subscribers-llvm-selectiondag @llvm/pr-subscribers-llvm-globalisel Author: Kazu Hirata (kazutakahirata) ChangesFull diff: https://github.com/llvm/llvm-project/pull/133603.diff 9 Files Affected:
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index f8afb42bf5535..85a6d67609798 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1477,8 +1477,7 @@ static uint64_t getOffsetFromIndices(const User &U, const DataLayout &DL) {
for (auto Idx : IVI->indices())
Indices.push_back(ConstantInt::get(Int32Ty, Idx));
} else {
- for (Value *Op : drop_begin(U.operands()))
- Indices.push_back(Op);
+ llvm::append_range(Indices, drop_begin(U.operands()));
}
return 8 * static_cast<uint64_t>(
@@ -2212,8 +2211,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
case Intrinsic::fake_use: {
SmallVector<llvm::SrcOp, 4> VRegs;
for (const auto &Arg : CI.args())
- for (auto VReg : getOrCreateVRegs(*Arg))
- VRegs.push_back(VReg);
+ llvm::append_range(VRegs, getOrCreateVRegs(*Arg));
MIRBuilder.buildInstr(TargetOpcode::FAKE_USE, {}, VRegs);
MF->setHasFakeUses(true);
return true;
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index c28f3c5518301..ac68eb55a6fd5 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -4906,8 +4906,7 @@ LegalizerHelper::fewerElementsVectorMultiEltType(
SmallVector<Register, 8> SplitPieces;
extractVectorParts(MI.getReg(UseIdx), NumElts, SplitPieces, MIRBuilder,
MRI);
- for (auto Reg : SplitPieces)
- InputOpsPieces[UseNo].push_back(Reg);
+ llvm::append_range(InputOpsPieces[UseNo], SplitPieces);
}
}
diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
index 9f11ccf21bd1f..c70c638dc016c 100644
--- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
+++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
@@ -4218,9 +4218,7 @@ std::optional<ValueIDNum> InstrRefBasedLDV::resolveDbgPHIsImpl(
}
// Sort PHIs to validate into RPO-order.
- SmallVector<LDVSSAPhi *, 8> SortedPHIs;
- for (auto &PHI : CreatedPHIs)
- SortedPHIs.push_back(PHI);
+ SmallVector<LDVSSAPhi *, 8> SortedPHIs(CreatedPHIs);
llvm::sort(SortedPHIs, [&](LDVSSAPhi *A, LDVSSAPhi *B) {
return BBToOrder[&A->getParent()->BB] < BBToOrder[&B->getParent()->BB];
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 173193bb6266c..aa2987b6710a3 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -2326,8 +2326,7 @@ bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
for (MCRegUnit Unit : TRI->regunits(MO.getReg())) {
for (const auto &MIRegs : SeenDbgInstrs.lookup(Unit)) {
auto &Regs = DbgValsToSinkMap[MIRegs.first];
- for (Register Reg : MIRegs.second)
- Regs.push_back(Reg);
+ llvm::append_range(Regs, MIRegs.second);
}
}
}
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index ac1e9fe1ca589..a5cd9fc7a5360 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2195,8 +2195,7 @@ MCRegister RAGreedy::tryLastChanceRecoloring(
if (tryRecoloringCandidates(RecoloringQueue, CurrentNewVRegs,
FixedRegisters, RecolorStack, Depth)) {
// Push the queued vregs into the main queue.
- for (Register NewVReg : CurrentNewVRegs)
- NewVRegs.push_back(NewVReg);
+ llvm::append_range(NewVRegs, CurrentNewVRegs);
// Do not mess up with the global assignment process.
// I.e., VirtReg must be unassigned.
if (VRM->hasPhys(ThisVirtReg)) {
diff --git a/llvm/lib/CodeGen/SelectOptimize.cpp b/llvm/lib/CodeGen/SelectOptimize.cpp
index b35f765c76489..00148b075134a 100644
--- a/llvm/lib/CodeGen/SelectOptimize.cpp
+++ b/llvm/lib/CodeGen/SelectOptimize.cpp
@@ -451,8 +451,7 @@ void SelectOptimizeImpl::optimizeSelectsInnerLoops(Function &F,
SmallVector<Loop *, 4> Loops(LI->begin(), LI->end());
// Need to check size on each iteration as we accumulate child loops.
for (unsigned long i = 0; i < Loops.size(); ++i)
- for (Loop *ChildL : Loops[i]->getSubLoops())
- Loops.push_back(ChildL);
+ llvm::append_range(Loops, Loops[i]->getSubLoops());
for (Loop *L : Loops) {
if (!L->isInnermost())
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 5182e4124f548..4b7a9127b3fc3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -1195,8 +1195,7 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
// Add rounding control registers as implicit def for function call.
if (II.isCall() && MF->getFunction().hasFnAttribute(Attribute::StrictFP)) {
ArrayRef<MCPhysReg> RCRegs = TLI->getRoundingControlRegisters();
- for (MCPhysReg Reg : RCRegs)
- UsedRegs.push_back(Reg);
+ llvm::append_range(UsedRegs, RCRegs);
}
// Finally mark unused registers as dead.
diff --git a/llvm/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h b/llvm/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h
index 4c6b3a5be416d..17086876ad537 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h
+++ b/llvm/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h
@@ -197,8 +197,7 @@ class SDDbgValue {
for (const SDDbgOperand &DbgOp : getLocationOps())
if (DbgOp.getKind() == SDDbgOperand::SDNODE)
Dependencies.push_back(DbgOp.getSDNode());
- for (SDNode *Node : getAdditionalDependencies())
- Dependencies.push_back(Node);
+ llvm::append_range(Dependencies, getAdditionalDependencies());
return Dependencies;
}
diff --git a/llvm/lib/CodeGen/WindowScheduler.cpp b/llvm/lib/CodeGen/WindowScheduler.cpp
index 78af6314e7b2d..95c86a9ac2668 100644
--- a/llvm/lib/CodeGen/WindowScheduler.cpp
+++ b/llvm/lib/CodeGen/WindowScheduler.cpp
@@ -283,8 +283,7 @@ void WindowScheduler::restoreMBB() {
MI.eraseFromParent();
}
// Restore MBB to the state before window scheduling.
- for (auto *MI : OriMIs)
- MBB->push_back(MI);
+ llvm::append_range(*MBB, OriMIs);
updateLiveIntervals();
}
|
kuhar
approved these changes
Mar 29, 2025
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/186/builds/7779 Here is the relevant piece of the build log for the reference |
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