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[RISCV] Add assembler support for Zvqdotq. (#132118)
Based on the 0.0.1 spec here https://github.com/riscv/riscv-dot-product/releases/tag/v0.0.1
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‎clang/test/Driver/print-supported-extensions-riscv.c

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@@ -190,6 +190,7 @@
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// CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions)
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// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
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// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
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// CHECK-NEXT: zvqdotq 0.0 'Zvqdotq' (Vector quad widening 4D Dot Product)
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// CHECK-NEXT: sdext 1.0 'Sdext' (External debugger)
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// CHECK-NEXT: sdtrig 1.0 'Sdtrig' (Debugger triggers)
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// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)

‎clang/test/Preprocessor/riscv-target-features.c

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// CHECK-NOT: __riscv_zvfbfmin {{.*$}}
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// CHECK-NOT: __riscv_zvfbfwma {{.*$}}
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// CHECK-NOT: __riscv_zvkgs {{.*$}}
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// CHECK-NOT: __riscv_zvqdotq {{.*$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32ia -E -dM %s \
@@ -1761,6 +1762,14 @@
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKGS-EXT %s
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// CHECK-ZVKGS-EXT: __riscv_zvkgs 7000{{$}}
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// RUN: %clang --target=riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zve32x_zvqdotq0p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVqdotq-EXT %s
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// RUN: %clang --target=riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zve32x_zvqdotq0p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVqdotq-EXT %s
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// CHECK-ZVqdotq-EXT: __riscv_zvqdotq 0{{$}}
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// RUN: %clang -target riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32izicfiss1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s

‎llvm/docs/RISCVUsage.rst

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@@ -337,6 +337,9 @@ The primary goal of experimental support is to assist in the process of ratifica
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``experimental-svukte``
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LLVM implements the `0.3 draft specification <https://github.com/riscv/riscv-isa-manual/pull/1564>`__.
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``experimental-zvqdotq``
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LLVM implements the `0.0.1 draft specification <https://github.com/riscv/riscv-dot-product/releases/tag/v0.0.1>`__.
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To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
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Vendor Extensions

‎llvm/docs/ReleaseNotes.md

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@@ -134,6 +134,7 @@ Changes to the RISC-V Backend
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extension.
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* Adds assembler support for the 'Zclsd` (Compressed Load/Store Pair Instructions)
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extension.
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* Adds experimental assembler support for Zvqdotq.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -820,6 +820,16 @@ def FeatureStdExtZvksc
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def FeatureStdExtZvksg
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: RISCVExtension<1, 0, "shorthand for 'Zvks' and 'Zvkg'",
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[FeatureStdExtZvks, FeatureStdExtZvkg]>;
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// Vector quad widening dot product
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def FeatureStdExtZvqdotq
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: RISCVExperimentalExtension<0, 0, "Vector quad widening 4D Dot Product",
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[FeatureStdExtZve32x]>;
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def HasStdExtZvqdotq : Predicate<"Subtarget->hasStdExtZvqdotq()">,
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AssemblerPredicate<(all_of FeatureStdExtZvqdotq),
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"'Zvqdotq' (Vector quad widening 4D Dot Product)">;
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// Vector instruction predicates
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def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">,

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

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@@ -2138,6 +2138,7 @@ include "RISCVInstrInfoZk.td"
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// Vector
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include "RISCVInstrInfoV.td"
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include "RISCVInstrInfoZvk.td"
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include "RISCVInstrInfoZvqdotq.td"
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// Integer
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include "RISCVInstrInfoZimop.td"

‎llvm/lib/Target/RISCV/RISCVInstrInfoZvqdotq.td

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//===-- RISCVInstrInfoZvqdot.td - 'Zvqdotq' instructions ---*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard 'Zvqdotq'
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// extension.
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// This version is still experimental as the 'Zvqdotq' extension hasn't been
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// ratified yet.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZvqdotq] in {
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def VQDOT_VV : VALUVV<0b101100, OPMVV, "vqdot.vv">;
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def VQDOT_VX : VALUVX<0b101100, OPMVX, "vqdot.vx">;
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def VQDOTU_VV : VALUVV<0b101000, OPMVV, "vqdotu.vv">;
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def VQDOTU_VX : VALUVX<0b101000, OPMVX, "vqdotu.vx">;
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def VQDOTSU_VV : VALUVV<0b101010, OPMVV, "vqdotsu.vv">;
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def VQDOTSU_VX : VALUVX<0b101010, OPMVX, "vqdotsu.vx">;
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def VQDOTUS_VX : VALUVX<0b101110, OPMVX, "vqdotus.vx">;
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} // Predicates = [HasStdExtZvqdotq]

‎llvm/test/CodeGen/RISCV/attributes.ll

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@@ -127,6 +127,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+zvksg %s -o - | FileCheck --check-prefix=RV32ZVKSG %s
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; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
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; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s
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; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvqdotq %s -o - | FileCheck --check-prefix=RV32ZVQDOTQ %s
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; RUN: llc -mtriple=riscv32 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV32ZVFH %s
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; RUN: llc -mtriple=riscv32 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
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; RUN: llc -mtriple=riscv32 -mattr=+zilsd %s -o - | FileCheck --check-prefix=RV32ZILSD %s
@@ -279,6 +280,7 @@
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; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvksg %s -o - | FileCheck --check-prefix=RV64ZVKSG %s
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; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
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; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
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; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvqdotq %s -o - | FileCheck --check-prefix=RV64ZVQDOTQ %s
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; RUN: llc -mtriple=riscv64 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV64ZVFH %s
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; RUN: llc -mtriple=riscv64 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
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; RUN: llc -mtriple=riscv64 -mattr=+zimop %s -o - | FileCheck --check-prefix=RV64ZIMOP %s
@@ -455,6 +457,7 @@
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; RV32ZVKSG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
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; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
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; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
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; RV32ZVQDOTQ: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqdotq0p0"
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; RV32ZVFH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0"
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; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
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; RV32ZILSD: .attribute 5, "rv32i2p1_zilsd1p0"
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; RV64ZVKSG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0"
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; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
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; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
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; RV64ZVQDOTQ: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqdotq0p0"
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; RV64ZVFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0"
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; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0"
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; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop1p0"

‎llvm/test/MC/RISCV/attribute-arch.s

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.attribute arch, "rv32i_zvkt1p0"
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# CHECK: attribute 5, "rv32i2p1_zvkt1p0"
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.attribute arch, "rv32i_zvqdotq0p0"
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# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqdotq0p0"
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.attribute arch, "rv32izbs1p0"
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# CHECK: attribute 5, "rv32i2p1_zbs1p0"
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# CHECK: attribute 5, "rv32i2p1_p0p14"
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.attribute arch, "rv64i_p0p14"
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# CHECK: attribute 5, "rv64i2p1_p0p14"
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# CHECK: attribute 5, "rv64i2p1_p0p14"

‎llvm/test/MC/RISCV/rvv/zvqdotq-invalid.s

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# RUN: not llvm-mc -triple=riscv64 --mattr=+experimental-zvqdotq %s 2>&1 \
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# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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vqdot.vv v0, v2, v4, v0.t
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# CHECK-ERROR: the destination vector register group cannot overlap the mask register
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# CHECK-ERROR-LABEL: vqdot.vv v0, v2, v4, v0.t
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vqdot.vx v0, v2, a0, v0.t
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# CHECK-ERROR: the destination vector register group cannot overlap the mask register
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# CHECK-ERROR-LABEL: vqdot.vx v0, v2, a0, v0.t

‎llvm/test/MC/RISCV/rvv/zvqdotq.s

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# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zvqdotq %s \
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# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
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# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvqdotq %s \
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# RUN: | llvm-objdump -d --mattr=+experimental-zvqdotq - \
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# RUN: | FileCheck %s --check-prefix=CHECK-INST
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# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvqdotq %s \
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# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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vqdot.vv v8, v4, v20, v0.t
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# CHECK-INST: vqdot.vv v8, v4, v20, v0.t
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# CHECK-ENCODING: [0x57,0x24,0x4a,0xb0]
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# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
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# CHECK-UNKNOWN: b04a2457 <unknown>
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vqdot.vv v8, v4, v20
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# CHECK-INST: vqdot.vv v8, v4, v20
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# CHECK-ENCODING: [0x57,0x24,0x4a,0xb2]
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# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
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# CHECK-UNKNOWN: b24a2457 <unknown>
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vqdotu.vv v8, v4, v20, v0.t
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# CHECK-INST: vqdotu.vv v8, v4, v20, v0.t
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# CHECK-ENCODING: [0x57,0x24,0x4a,0xa0]
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# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
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# CHECK-UNKNOWN: a04a2457 <unknown>
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vqdotu.vv v8, v4, v20
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# CHECK-INST: vqdotu.vv v8, v4, v20
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# CHECK-ENCODING: [0x57,0x24,0x4a,0xa2]
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# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
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# CHECK-UNKNOWN: a24a2457 <unknown>
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vqdotsu.vv v8, v4, v20, v0.t
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# CHECK-INST: vqdotsu.vv v8, v4, v20, v0.t
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# CHECK-ENCODING: [0x57,0x24,0x4a,0xa8]
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# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
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# CHECK-UNKNOWN: a84a2457 <unknown>
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vqdotsu.vv v8, v4, v20
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# CHECK-INST: vqdotsu.vv v8, v4, v20
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# CHECK-ENCODING: [0x57,0x24,0x4a,0xaa]
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# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
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# CHECK-UNKNOWN: aa4a2457 <unknown>
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vqdot.vx v8, v4, s4, v0.t
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# CHECK-INST: vqdot.vx v8, v4, s4, v0.t
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# CHECK-ENCODING: [0x57,0x64,0x4a,0xb0]
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# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
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# CHECK-UNKNOWN: b04a6457 <unknown>
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vqdot.vx v8, v4, s4
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# CHECK-INST: vqdot.vx v8, v4, s4
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# CHECK-ENCODING: [0x57,0x64,0x4a,0xb2]
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# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
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# CHECK-UNKNOWN: b24a6457 <unknown>
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vqdotu.vx v8, v4, s4, v0.t
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# CHECK-INST: vqdotu.vx v8, v4, s4, v0.t
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# CHECK-ENCODING: [0x57,0x64,0x4a,0xa0]
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# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
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# CHECK-UNKNOWN: a04a6457 <unknown>
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vqdotu.vx v8, v4, s4
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# CHECK-INST: vqdotu.vx v8, v4, s4
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# CHECK-ENCODING: [0x57,0x64,0x4a,0xa2]
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# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
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# CHECK-UNKNOWN: a24a6457 <unknown>
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vqdotsu.vx v8, v4, s4, v0.t
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# CHECK-INST: vqdotsu.vx v8, v4, s4, v0.t
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# CHECK-ENCODING: [0x57,0x64,0x4a,0xa8]
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# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
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# CHECK-UNKNOWN: a84a6457 <unknown>
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vqdotsu.vx v8, v4, s4
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# CHECK-INST: vqdotsu.vx v8, v4, s4
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# CHECK-ENCODING: [0x57,0x64,0x4a,0xaa]
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# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
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# CHECK-UNKNOWN: aa4a6457 <unknown>
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vqdotus.vx v8, v4, s4, v0.t
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# CHECK-INST: vqdotus.vx v8, v4, s4, v0.t
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# CHECK-ENCODING: [0x57,0x64,0x4a,0xb8]
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# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
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# CHECK-UNKNOWN: b84a6457 <unknown>
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vqdotus.vx v8, v4, s4
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# CHECK-INST: vqdotus.vx v8, v4, s4
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# CHECK-ENCODING: [0x57,0x64,0x4a,0xba]
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# CHECK-ERROR: instruction requires the following: 'Zvqdotq' (Vector quad widening 4D Dot Product){{$}}
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# CHECK-UNKNOWN: ba4a6457 <unknown>

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

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@@ -1136,6 +1136,7 @@ Experimental extensions
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zalasr 0.1
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zvbc32e 0.7
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zvkgs 0.7
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zvqdotq 0.0
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sdext 1.0
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sdtrig 1.0
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smctr 1.0

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