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[AArch64]Fix FEAT_SME_LUTv2 to have FEAT_SME2 implemented. (#110474)
According to [1] "If FEAT_SME_LUTv2 is implemented, then FEAT_SME2 is implemented." The LUTI4[2] not strided and MOVT[3] need FEAT_SME_LUTv2 to be defined. [1]https://developer.arm.com/documentation/109697/0100/Feature-descriptions/The-Armv9-5-architecture-extension?lang=en#md462-the-armv95-architecture-extension__FEAT_SME_LUTv2 [2]https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions/LUTI4--four-registers--8-bit---Lookup-table-read-with-4-bit-indexes-and-8-bit-elements- [3]https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions/MOVT--vector-to-table---Move-vector-register-to-ZT0-
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‎clang/include/clang/Basic/arm_sme.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -818,7 +818,7 @@ multiclass ZAReadzArray<string vg_num>{
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defm SVREADZ_VG2 : ZAReadzArray<"2">;
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defm SVREADZ_VG4 : ZAReadzArray<"4">;
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821-
let SMETargetGuard = "sme2,sme-lutv2" in {
821+
let SMETargetGuard = "sme-lutv2" in {
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def SVWRITE_LANE_ZT : SInst<"svwrite_lane_zt[_{d}]", "vidi", "cUcsUsiUilUlfhdb", MergeNone, "aarch64_sme_write_lane_zt", [IsStreaming, IsInOutZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck1_3>]>;
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def SVWRITE_ZT : SInst<"svwrite_zt[_{d}]", "vid", "cUcsUsiUilUlfhdb", MergeNone, "aarch64_sme_write_zt", [IsStreaming, IsOutZT0], [ImmCheck<0, ImmCheck0_0>]>;
824824
def SVLUTI4_ZT_X4 : SInst<"svluti4_zt_{d}_x4", "4i2.u", "cUc", MergeNone, "aarch64_sme_luti4_zt_x4", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>]>;

‎clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_write_lane_zt.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
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3-
// RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
4-
// RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
5-
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
6-
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
7-
// RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
3+
// RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature +sme2 -target-feature +sme -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
4+
// RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature +sme2 -target-feature +sme -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
5+
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
6+
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
7+
// RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
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99
// REQUIRES: aarch64-registered-target
1010

‎llvm/lib/Target/AArch64/AArch64Features.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -501,7 +501,7 @@ def FeatureSSVE_FP8DOT2 : ExtensionWithMArch<"ssve-fp8dot2", "SSVE_FP8DOT2", "FE
501501
"Enable SVE2 FP8 2-way dot product instructions", [FeatureSSVE_FP8DOT4]>;
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503503
def FeatureSME_LUTv2 : ExtensionWithMArch<"sme-lutv2", "SME_LUTv2", "FEAT_SME_LUTv2",
504-
"Enable Scalable Matrix Extension (SME) LUTv2 instructions">;
504+
"Enable Scalable Matrix Extension (SME) LUTv2 instructions", [FeatureSME2]>;
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506506
def FeatureSMEF8F32 : ExtensionWithMArch<"sme-f8f32", "SMEF8F32", "FEAT_SME_F8F32",
507507
"Enable Scalable Matrix Extension (SME) F8F32 instructions", [FeatureSME2, FeatureFP8]>;

‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -938,10 +938,11 @@ defm FAMAX_4Z4Z : sme2_fp_sve_destructive_vector_vg4_multi<"famax", 0b0010100>;
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defm FAMIN_4Z4Z : sme2_fp_sve_destructive_vector_vg4_multi<"famin", 0b0010101>;
939939
} //[HasSME2, HasFAMINMAX]
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941-
let Predicates = [HasSME2, HasSME_LUTv2] in {
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let Predicates = [HasSME_LUTv2] in {
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defm MOVT_TIZ : sme2_movt_zt_to_zt<"movt", 0b0011111, int_aarch64_sme_write_lane_zt, int_aarch64_sme_write_zt>;
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def LUTI4_4ZZT2Z : sme2_luti4_vector_vg4<0b00, 0b00,"luti4">;
944-
} //[HasSME2, HasSME_LUTv2]
945+
} //[HasSME_LUTv2]
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946947
let Predicates = [HasSME2p1, HasSME_LUTv2] in {
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def LUTI4_S_4ZZT2Z : sme2_luti4_vector_vg4_strided<0b00, 0b00, "luti4">;

‎llvm/test/MC/AArch64/FP8/directive-arch-negative.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -51,5 +51,5 @@ luti2 z0.h, { z0.h }, z0[0]
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.arch armv9-a+sme-lutv2
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.arch armv9-a+nosme-lutv2
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luti4 { z0.b - z3.b }, zt0, { z0, z1 }
54-
// CHECK: error: instruction requires: sme2 sme-lutv2
54+
// CHECK: error: instruction requires: sme-lutv2
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// CHECK: luti4 { z0.b - z3.b }, zt0, { z0, z1 }

‎llvm/test/MC/AArch64/FP8_SME2/lut.s

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,33 +1,33 @@
1-
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme2p1,+sme-lutv2 < %s \
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-lutv2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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7-
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme2p1,+sme-lutv2 < %s \
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// RUN: | llvm-objdump -d --mattr=+sme2,+sme2p1,+sme-lutv2 --no-print-imm-hex - \
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-lutv2 < %s \
8+
// RUN: | llvm-objdump -d --mattr=+sme2p1,+sme-lutv2 --no-print-imm-hex - \
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// RUN: | FileCheck %s --check-prefix=CHECK-INST
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11-
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme2p1,+sme-lutv2 < %s \
11+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-lutv2 < %s \
1212
// RUN: | llvm-objdump -d --mattr=-sme-lutv2 --no-print-imm-hex - \
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// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
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1515
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
16-
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme2p1,+sme-lutv2 < %s \
16+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-lutv2 < %s \
1717
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
18-
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+sme2p1,+sme-lutv2 -disassemble -show-encoding \
18+
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-lutv2 -disassemble -show-encoding \
1919
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
2020

2121
luti4 {z0.b-z3.b}, zt0, {z0-z1} // 11000000-10001011-00000000-00000000
2222
// CHECK-INST: luti4 { z0.b - z3.b }, zt0, { z0, z1 }
2323
// CHECK-ENCODING: [0x00,0x00,0x8b,0xc0]
24-
// CHECK-ERROR: instruction requires: sme2 sme-lutv2
24+
// CHECK-ERROR: instruction requires: sme-lutv2
2525
// CHECK-UNKNOWN: c08b0000 <unknown>
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2727
luti4 {z28.b-z31.b}, zt0, {z30-z31} // 11000000-10001011-00000011-11011100
2828
// CHECK-INST: luti4 { z28.b - z31.b }, zt0, { z30, z31 }
2929
// CHECK-ENCODING: [0xdc,0x03,0x8b,0xc0]
30-
// CHECK-ERROR: instruction requires: sme2 sme-lutv2
30+
// CHECK-ERROR: instruction requires: sme-lutv2
3131
// CHECK-UNKNOWN: c08b03dc <unknown>
3232

3333
// Strided

‎llvm/test/MC/AArch64/FP8_SME2/movt-diagnostics.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11

2-
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-lutv2 2>&1 < %s | FileCheck %s
2+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-lutv2 2>&1 < %s | FileCheck %s
33
// --------------------------------------------------------------------------//
44
// Invalid vector select register
55
movt z0, z31

‎llvm/test/MC/AArch64/FP8_SME2/movt.s

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,14 @@
1-
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-lutv2 < %s \
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-lutv2 < %s \
22
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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44
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
55
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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7-
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-lutv2 < %s \
8-
// RUN: | llvm-objdump -d --mattr=+sme2,+sme-lutv2 --no-print-imm-hex - \
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-lutv2 < %s \
8+
// RUN: | llvm-objdump -d --mattr=+sme-lutv2 --no-print-imm-hex - \
99
// RUN: | FileCheck %s --check-prefix=CHECK-INST
1010

11-
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-lutv2 < %s \
11+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-lutv2 < %s \
1212
// RUN: | llvm-objdump -d --mattr=-sme-lutv2 --no-print-imm-hex - \
1313
// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
1414

@@ -21,11 +21,11 @@
2121
movt zt0, z0 // 11000000-01001111-00000011-11100000
2222
// CHECK-INST: movt zt0, z0
2323
// CHECK-ENCODING: [0xe0,0x03,0x4f,0xc0]
24-
// CHECK-ERROR: instruction requires: sme2 sme-lutv2
24+
// CHECK-ERROR: instruction requires: sme-lutv2
2525
// CHECK-UNKNOWN: c04f03e0 <unknown>
2626

2727
movt zt0[3, mul vl], z31 // 11000000-01001111-00110011-11111111
2828
// CHECK-INST: movt zt0[3, mul vl], z31
2929
// CHECK-ENCODING: [0xff,0x33,0x4f,0xc0]
30-
// CHECK-ERROR: instruction requires: sme2 sme-lutv2
30+
// CHECK-ERROR: instruction requires: sme-lutv2
3131
// CHECK-UNKNOWN: c04f33ff <unknown>

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