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[AArch64]Fix FEAT_SME_LUTv2 to have FEAT_SME2 implemented. #110474

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Merged
merged 5 commits into from
Oct 4, 2024
Merged

[AArch64]Fix FEAT_SME_LUTv2 to have FEAT_SME2 implemented. #110474

merged 5 commits into from
Oct 4, 2024

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CarolineConcatto
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@CarolineConcatto CarolineConcatto commented Sep 30, 2024 •
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@llvmbot llvmbot added backend:AArch64 mc Machine (object) code labels Sep 30, 2024
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llvmbot commented Sep 30, 2024 •
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@llvm/pr-subscribers-clang

@llvm/pr-subscribers-mc

Author: None (CarolineConcatto)

Changes

According to [1]
"If FEAT_SME_LUTv2 is implemented, then FEAT_SME2 is implemented." The LUTI4[2] not strided and MOVT[2] need FEAT_SME_LUTv2 to be defined.

[1]https://developer.arm.com/documentation/109697/0100/Feature-descriptions/The-Armv9-5-architecture-extension?lang=en#md462-the-armv95-architecture-extension__FEAT_SME_LUTv2 [2]https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions/LUTI4--four-registers--8-bit---Lookup-table-read-with-4-bit-indexes-and-8-bit-elements- [3]https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions/MOVT--vector-to-table---Move-vector-register-to-ZT0-

Full diff: https://github.com/llvm/llvm-project/pull/110474.diff

6 Files Affected:

  • (modified) llvm/lib/Target/AArch64/AArch64Features.td (+1-1)
  • (modified) llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td (+2-2)
  • (modified) llvm/test/MC/AArch64/FP8/directive-arch-negative.s (+1-1)
  • (modified) llvm/test/MC/AArch64/FP8_SME2/lut.s (+8-8)
  • (modified) llvm/test/MC/AArch64/FP8_SME2/movt-diagnostics.s (+1-1)
  • (modified) llvm/test/MC/AArch64/FP8_SME2/movt.s (+6-6)
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 69d6b02fefffe9..5c37ced0158330 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -501,7 +501,7 @@ def FeatureSSVE_FP8DOT2 : ExtensionWithMArch<"ssve-fp8dot2", "SSVE_FP8DOT2", "FE
   "Enable SVE2 FP8 2-way dot product instructions", [FeatureSSVE_FP8DOT4]>;
 
 def FeatureSME_LUTv2 : ExtensionWithMArch<"sme-lutv2", "SME_LUTv2", "FEAT_SME_LUTv2",
-  "Enable Scalable Matrix Extension (SME) LUTv2 instructions">;
+  "Enable Scalable Matrix Extension (SME) LUTv2 instructions", [FeatureSME2]>;
 
 def FeatureSMEF8F32 : ExtensionWithMArch<"sme-f8f32", "SMEF8F32", "FEAT_SME_F8F32",
   "Enable Scalable Matrix Extension (SME) F8F32 instructions", [FeatureSME2, FeatureFP8]>;
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index ebe4121c944b1e..a750a34042d44c 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -938,10 +938,10 @@ defm FAMAX_4Z4Z : sme2_fp_sve_destructive_vector_vg4_multi<"famax", 0b0010100>;
 defm FAMIN_4Z4Z : sme2_fp_sve_destructive_vector_vg4_multi<"famin", 0b0010101>;
 } //[HasSME2, HasFAMINMAX]
 
-let Predicates = [HasSME2, HasSME_LUTv2] in {
+let Predicates = [HasSME_LUTv2] in {
 defm MOVT : sme2_movt_zt_to_zt<"movt",  0b0011111>;
 def LUTI4_4ZZT2Z    : sme2_luti4_vector_vg4<0b00, 0b00,"luti4">;
-} //[HasSME2, HasSME_LUTv2]
+} //[HasSME_LUTv2]
 
 let Predicates = [HasSME2p1, HasSME_LUTv2] in {
 def LUTI4_S_4ZZT2Z  : sme2_luti4_vector_vg4_strided<0b00, 0b00, "luti4">;
diff --git a/llvm/test/MC/AArch64/FP8/directive-arch-negative.s b/llvm/test/MC/AArch64/FP8/directive-arch-negative.s
index c4d8dbf44b03b6..34fdb74fe1f370 100644
--- a/llvm/test/MC/AArch64/FP8/directive-arch-negative.s
+++ b/llvm/test/MC/AArch64/FP8/directive-arch-negative.s
@@ -51,5 +51,5 @@ luti2  z0.h, { z0.h }, z0[0]
 .arch armv9-a+sme-lutv2
 .arch armv9-a+nosme-lutv2
 luti4  { z0.b - z3.b }, zt0, { z0, z1 }
-// CHECK: error: instruction requires: sme2 sme-lutv2
+// CHECK: error: instruction requires: sme-lutv2
 // CHECK: luti4  { z0.b - z3.b }, zt0, { z0, z1 }
diff --git a/llvm/test/MC/AArch64/FP8_SME2/lut.s b/llvm/test/MC/AArch64/FP8_SME2/lut.s
index 96c88f5da9a699..ae17ae42a1a945 100644
--- a/llvm/test/MC/AArch64/FP8_SME2/lut.s
+++ b/llvm/test/MC/AArch64/FP8_SME2/lut.s
@@ -1,33 +1,33 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme2p1,+sme-lutv2 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-lutv2 < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme2p1,+sme-lutv2 < %s \
-// RUN:        | llvm-objdump -d --mattr=+sme2,+sme2p1,+sme-lutv2 --no-print-imm-hex - \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-lutv2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2p1,+sme-lutv2 --no-print-imm-hex - \
 // RUN:        | FileCheck %s --check-prefix=CHECK-INST
 
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme2p1,+sme-lutv2 < %s \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-lutv2 < %s \
 // RUN:        | llvm-objdump -d --mattr=-sme-lutv2 --no-print-imm-hex - \
 // RUN:        | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 // Disassemble encoding and check the re-encoding (-show-encoding) matches.
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme2p1,+sme-lutv2 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-lutv2 < %s \
 // RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
-// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2,+sme2p1,+sme-lutv2 -disassemble -show-encoding \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-lutv2 -disassemble -show-encoding \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 
 luti4   {z0.b-z3.b}, zt0, {z0-z1}  // 11000000-10001011-00000000-00000000
 // CHECK-INST: luti4   { z0.b - z3.b }, zt0, { z0, z1 }
 // CHECK-ENCODING: [0x00,0x00,0x8b,0xc0]
-// CHECK-ERROR: instruction requires: sme2 sme-lutv2
+// CHECK-ERROR: instruction requires: sme-lutv2
 // CHECK-UNKNOWN: c08b0000 <unknown>
 
 luti4   {z28.b-z31.b}, zt0, {z30-z31}  // 11000000-10001011-00000011-11011100
 // CHECK-INST: luti4   { z28.b - z31.b }, zt0, { z30, z31 }
 // CHECK-ENCODING: [0xdc,0x03,0x8b,0xc0]
-// CHECK-ERROR: instruction requires: sme2 sme-lutv2
+// CHECK-ERROR: instruction requires: sme-lutv2
 // CHECK-UNKNOWN: c08b03dc <unknown>
 
 // Strided
diff --git a/llvm/test/MC/AArch64/FP8_SME2/movt-diagnostics.s b/llvm/test/MC/AArch64/FP8_SME2/movt-diagnostics.s
index ba453892112156..d3f334a3089b43 100644
--- a/llvm/test/MC/AArch64/FP8_SME2/movt-diagnostics.s
+++ b/llvm/test/MC/AArch64/FP8_SME2/movt-diagnostics.s
@@ -1,5 +1,5 @@
 
-// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-lutv2  2>&1 < %s | FileCheck %s
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-lutv2  2>&1 < %s | FileCheck %s
 // --------------------------------------------------------------------------//
 // Invalid vector select register
 movt   z0, z31
diff --git a/llvm/test/MC/AArch64/FP8_SME2/movt.s b/llvm/test/MC/AArch64/FP8_SME2/movt.s
index fa6502e138ab65..aa601fb3192773 100644
--- a/llvm/test/MC/AArch64/FP8_SME2/movt.s
+++ b/llvm/test/MC/AArch64/FP8_SME2/movt.s
@@ -1,14 +1,14 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-lutv2 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-lutv2 < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-lutv2 < %s \
-// RUN:        | llvm-objdump -d --mattr=+sme2,+sme-lutv2 --no-print-imm-hex - \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-lutv2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme-lutv2 --no-print-imm-hex - \
 // RUN:        | FileCheck %s --check-prefix=CHECK-INST
 
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-lutv2 < %s \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-lutv2 < %s \
 // RUN:        | llvm-objdump -d --mattr=-sme-lutv2 --no-print-imm-hex - \
 // RUN:        | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
@@ -21,11 +21,11 @@
 movt    zt0, z0  // 11000000-01001111-00000011-11100000
 // CHECK-INST: movt    zt0, z0
 // CHECK-ENCODING: [0xe0,0x03,0x4f,0xc0]
-// CHECK-ERROR: instruction requires: sme2 sme-lutv2
+// CHECK-ERROR: instruction requires: sme-lutv2
 // CHECK-UNKNOWN: c04f03e0 <unknown>
 
 movt    zt0[3, mul vl], z31  // 11000000-01001111-00110011-11111111
 // CHECK-INST: movt    zt0[3, mul vl], z31
 // CHECK-ENCODING: [0xff,0x33,0x4f,0xc0]
-// CHECK-ERROR: instruction requires: sme2 sme-lutv2
+// CHECK-ERROR: instruction requires: sme-lutv2
 // CHECK-UNKNOWN: c04f33ff <unknown>

@llvmbot
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llvmbot commented Sep 30, 2024

@llvm/pr-subscribers-backend-aarch64

Author: None (CarolineConcatto)

Changes

According to [1]
"If FEAT_SME_LUTv2 is implemented, then FEAT_SME2 is implemented." The LUTI4[2] not strided and MOVT[2] need FEAT_SME_LUTv2 to be defined.

[1]https://developer.arm.com/documentation/109697/0100/Feature-descriptions/The-Armv9-5-architecture-extension?lang=en#md462-the-armv95-architecture-extension__FEAT_SME_LUTv2 [2]https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions/LUTI4--four-registers--8-bit---Lookup-table-read-with-4-bit-indexes-and-8-bit-elements- [3]https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions/MOVT--vector-to-table---Move-vector-register-to-ZT0-

Full diff: https://github.com/llvm/llvm-project/pull/110474.diff

6 Files Affected:

  • (modified) llvm/lib/Target/AArch64/AArch64Features.td (+1-1)
  • (modified) llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td (+2-2)
  • (modified) llvm/test/MC/AArch64/FP8/directive-arch-negative.s (+1-1)
  • (modified) llvm/test/MC/AArch64/FP8_SME2/lut.s (+8-8)
  • (modified) llvm/test/MC/AArch64/FP8_SME2/movt-diagnostics.s (+1-1)
  • (modified) llvm/test/MC/AArch64/FP8_SME2/movt.s (+6-6)
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 69d6b02fefffe9..5c37ced0158330 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -501,7 +501,7 @@ def FeatureSSVE_FP8DOT2 : ExtensionWithMArch<"ssve-fp8dot2", "SSVE_FP8DOT2", "FE
   "Enable SVE2 FP8 2-way dot product instructions", [FeatureSSVE_FP8DOT4]>;
 
 def FeatureSME_LUTv2 : ExtensionWithMArch<"sme-lutv2", "SME_LUTv2", "FEAT_SME_LUTv2",
-  "Enable Scalable Matrix Extension (SME) LUTv2 instructions">;
+  "Enable Scalable Matrix Extension (SME) LUTv2 instructions", [FeatureSME2]>;
 
 def FeatureSMEF8F32 : ExtensionWithMArch<"sme-f8f32", "SMEF8F32", "FEAT_SME_F8F32",
   "Enable Scalable Matrix Extension (SME) F8F32 instructions", [FeatureSME2, FeatureFP8]>;
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index ebe4121c944b1e..a750a34042d44c 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -938,10 +938,10 @@ defm FAMAX_4Z4Z : sme2_fp_sve_destructive_vector_vg4_multi<"famax", 0b0010100>;
 defm FAMIN_4Z4Z : sme2_fp_sve_destructive_vector_vg4_multi<"famin", 0b0010101>;
 } //[HasSME2, HasFAMINMAX]
 
-let Predicates = [HasSME2, HasSME_LUTv2] in {
+let Predicates = [HasSME_LUTv2] in {
 defm MOVT : sme2_movt_zt_to_zt<"movt",  0b0011111>;
 def LUTI4_4ZZT2Z    : sme2_luti4_vector_vg4<0b00, 0b00,"luti4">;
-} //[HasSME2, HasSME_LUTv2]
+} //[HasSME_LUTv2]
 
 let Predicates = [HasSME2p1, HasSME_LUTv2] in {
 def LUTI4_S_4ZZT2Z  : sme2_luti4_vector_vg4_strided<0b00, 0b00, "luti4">;
diff --git a/llvm/test/MC/AArch64/FP8/directive-arch-negative.s b/llvm/test/MC/AArch64/FP8/directive-arch-negative.s
index c4d8dbf44b03b6..34fdb74fe1f370 100644
--- a/llvm/test/MC/AArch64/FP8/directive-arch-negative.s
+++ b/llvm/test/MC/AArch64/FP8/directive-arch-negative.s
@@ -51,5 +51,5 @@ luti2  z0.h, { z0.h }, z0[0]
 .arch armv9-a+sme-lutv2
 .arch armv9-a+nosme-lutv2
 luti4  { z0.b - z3.b }, zt0, { z0, z1 }
-// CHECK: error: instruction requires: sme2 sme-lutv2
+// CHECK: error: instruction requires: sme-lutv2
 // CHECK: luti4  { z0.b - z3.b }, zt0, { z0, z1 }
diff --git a/llvm/test/MC/AArch64/FP8_SME2/lut.s b/llvm/test/MC/AArch64/FP8_SME2/lut.s
index 96c88f5da9a699..ae17ae42a1a945 100644
--- a/llvm/test/MC/AArch64/FP8_SME2/lut.s
+++ b/llvm/test/MC/AArch64/FP8_SME2/lut.s
@@ -1,33 +1,33 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme2p1,+sme-lutv2 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-lutv2 < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme2p1,+sme-lutv2 < %s \
-// RUN:        | llvm-objdump -d --mattr=+sme2,+sme2p1,+sme-lutv2 --no-print-imm-hex - \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-lutv2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2p1,+sme-lutv2 --no-print-imm-hex - \
 // RUN:        | FileCheck %s --check-prefix=CHECK-INST
 
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme2p1,+sme-lutv2 < %s \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-lutv2 < %s \
 // RUN:        | llvm-objdump -d --mattr=-sme-lutv2 --no-print-imm-hex - \
 // RUN:        | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 // Disassemble encoding and check the re-encoding (-show-encoding) matches.
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme2p1,+sme-lutv2 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-lutv2 < %s \
 // RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
-// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2,+sme2p1,+sme-lutv2 -disassemble -show-encoding \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-lutv2 -disassemble -show-encoding \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 
 luti4   {z0.b-z3.b}, zt0, {z0-z1}  // 11000000-10001011-00000000-00000000
 // CHECK-INST: luti4   { z0.b - z3.b }, zt0, { z0, z1 }
 // CHECK-ENCODING: [0x00,0x00,0x8b,0xc0]
-// CHECK-ERROR: instruction requires: sme2 sme-lutv2
+// CHECK-ERROR: instruction requires: sme-lutv2
 // CHECK-UNKNOWN: c08b0000 <unknown>
 
 luti4   {z28.b-z31.b}, zt0, {z30-z31}  // 11000000-10001011-00000011-11011100
 // CHECK-INST: luti4   { z28.b - z31.b }, zt0, { z30, z31 }
 // CHECK-ENCODING: [0xdc,0x03,0x8b,0xc0]
-// CHECK-ERROR: instruction requires: sme2 sme-lutv2
+// CHECK-ERROR: instruction requires: sme-lutv2
 // CHECK-UNKNOWN: c08b03dc <unknown>
 
 // Strided
diff --git a/llvm/test/MC/AArch64/FP8_SME2/movt-diagnostics.s b/llvm/test/MC/AArch64/FP8_SME2/movt-diagnostics.s
index ba453892112156..d3f334a3089b43 100644
--- a/llvm/test/MC/AArch64/FP8_SME2/movt-diagnostics.s
+++ b/llvm/test/MC/AArch64/FP8_SME2/movt-diagnostics.s
@@ -1,5 +1,5 @@
 
-// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-lutv2  2>&1 < %s | FileCheck %s
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-lutv2  2>&1 < %s | FileCheck %s
 // --------------------------------------------------------------------------//
 // Invalid vector select register
 movt   z0, z31
diff --git a/llvm/test/MC/AArch64/FP8_SME2/movt.s b/llvm/test/MC/AArch64/FP8_SME2/movt.s
index fa6502e138ab65..aa601fb3192773 100644
--- a/llvm/test/MC/AArch64/FP8_SME2/movt.s
+++ b/llvm/test/MC/AArch64/FP8_SME2/movt.s
@@ -1,14 +1,14 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-lutv2 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-lutv2 < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-lutv2 < %s \
-// RUN:        | llvm-objdump -d --mattr=+sme2,+sme-lutv2 --no-print-imm-hex - \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-lutv2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme-lutv2 --no-print-imm-hex - \
 // RUN:        | FileCheck %s --check-prefix=CHECK-INST
 
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-lutv2 < %s \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-lutv2 < %s \
 // RUN:        | llvm-objdump -d --mattr=-sme-lutv2 --no-print-imm-hex - \
 // RUN:        | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
@@ -21,11 +21,11 @@
 movt    zt0, z0  // 11000000-01001111-00000011-11100000
 // CHECK-INST: movt    zt0, z0
 // CHECK-ENCODING: [0xe0,0x03,0x4f,0xc0]
-// CHECK-ERROR: instruction requires: sme2 sme-lutv2
+// CHECK-ERROR: instruction requires: sme-lutv2
 // CHECK-UNKNOWN: c04f03e0 <unknown>
 
 movt    zt0[3, mul vl], z31  // 11000000-01001111-00110011-11111111
 // CHECK-INST: movt    zt0[3, mul vl], z31
 // CHECK-ENCODING: [0xff,0x33,0x4f,0xc0]
-// CHECK-ERROR: instruction requires: sme2 sme-lutv2
+// CHECK-ERROR: instruction requires: sme-lutv2
 // CHECK-UNKNOWN: c04f33ff <unknown>

jthackray
jthackray approved these changes Sep 30, 2024
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LGTM.

SpencerAbson
SpencerAbson approved these changes Sep 30, 2024
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Great, thanks.

@llvmbot llvmbot added clang Clang issues not falling into any other category clang:frontend Language frontend issues, e.g. anything involving "Sema" labels Oct 3, 2024
@CarolineConcatto CarolineConcatto merged commit ef8d506 into llvm:main Oct 4, 2024
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@jthackray jthackray jthackray approved these changes

@SpencerAbson SpencerAbson SpencerAbson approved these changes

@momchil-velikov momchil-velikov Awaiting requested review from momchil-velikov

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backend:AArch64 clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category mc Machine (object) code
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@CarolineConcatto @llvmbot @jthackray @SpencerAbson