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[AArch64]Fix FEAT_SME_LUTv2 to have FEAT_SME2 implemented. #110474

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Merged
merged 5 commits into from
Oct 4, 2024
Merged

[AArch64]Fix FEAT_SME_LUTv2 to have FEAT_SME2 implemented. #110474

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3dba902
[AArch64]Fix FEAT_SME_LUTv2 to have FEAT_SME2 implemented.
CarolineConcatto Sep 23, 2024
4771b1e
Merge branch 'main' into fix-sme-lutv2
CarolineConcatto Oct 1, 2024
84d02b2
Remove sme2 dependency from sme-lutv2 intrinsics
CarolineConcatto Oct 3, 2024
bdcc879
Update acle_sme2_write_lane_zt.c
CarolineConcatto Oct 3, 2024
7b0ce96
Update acle_sme2_luti4_zt.c
CarolineConcatto Oct 3, 2024
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2 changes: 1 addition & 1 deletion clang/include/clang/Basic/arm_sme.td
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Expand Up @@ -818,7 +818,7 @@ multiclass ZAReadzArray<string vg_num>{
defm SVREADZ_VG2 : ZAReadzArray<"2">;
defm SVREADZ_VG4 : ZAReadzArray<"4">;

let SMETargetGuard = "sme2,sme-lutv2" in {
let SMETargetGuard = "sme-lutv2" in {
def SVWRITE_LANE_ZT : SInst<"svwrite_lane_zt[_{d}]", "vidi", "cUcsUsiUilUlfhdb", MergeNone, "aarch64_sme_write_lane_zt", [IsStreaming, IsInOutZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck1_3>]>;
def SVWRITE_ZT : SInst<"svwrite_zt[_{d}]", "vid", "cUcsUsiUilUlfhdb", MergeNone, "aarch64_sme_write_zt", [IsStreaming, IsOutZT0], [ImmCheck<0, ImmCheck0_0>]>;
def SVLUTI4_ZT_X4 : SInst<"svluti4_zt_{d}_x4", "4i2.u", "cUc", MergeNone, "aarch64_sme_luti4_zt_x4", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>]>;
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10 changes: 5 additions & 5 deletions clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_write_lane_zt.c
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@@ -1,10 +1,10 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5

// RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
// RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature +sme2 -target-feature +sme -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature +sme2 -target-feature +sme -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s

// REQUIRES: aarch64-registered-target

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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64Features.td
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Expand Up @@ -501,7 +501,7 @@ def FeatureSSVE_FP8DOT2 : ExtensionWithMArch<"ssve-fp8dot2", "SSVE_FP8DOT2", "FE
"Enable SVE2 FP8 2-way dot product instructions", [FeatureSSVE_FP8DOT4]>;

def FeatureSME_LUTv2 : ExtensionWithMArch<"sme-lutv2", "SME_LUTv2", "FEAT_SME_LUTv2",
"Enable Scalable Matrix Extension (SME) LUTv2 instructions">;
"Enable Scalable Matrix Extension (SME) LUTv2 instructions", [FeatureSME2]>;

def FeatureSMEF8F32 : ExtensionWithMArch<"sme-f8f32", "SMEF8F32", "FEAT_SME_F8F32",
"Enable Scalable Matrix Extension (SME) F8F32 instructions", [FeatureSME2, FeatureFP8]>;
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5 changes: 3 additions & 2 deletions llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
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Expand Up @@ -938,10 +938,11 @@ defm FAMAX_4Z4Z : sme2_fp_sve_destructive_vector_vg4_multi<"famax", 0b0010100>;
defm FAMIN_4Z4Z : sme2_fp_sve_destructive_vector_vg4_multi<"famin", 0b0010101>;
} //[HasSME2, HasFAMINMAX]

let Predicates = [HasSME2, HasSME_LUTv2] in {

let Predicates = [HasSME_LUTv2] in {
defm MOVT_TIZ : sme2_movt_zt_to_zt<"movt", 0b0011111, int_aarch64_sme_write_lane_zt, int_aarch64_sme_write_zt>;
def LUTI4_4ZZT2Z : sme2_luti4_vector_vg4<0b00, 0b00,"luti4">;
} //[HasSME2, HasSME_LUTv2]
} //[HasSME_LUTv2]

let Predicates = [HasSME2p1, HasSME_LUTv2] in {
def LUTI4_S_4ZZT2Z : sme2_luti4_vector_vg4_strided<0b00, 0b00, "luti4">;
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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/FP8/directive-arch-negative.s
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Expand Up @@ -51,5 +51,5 @@ luti2 z0.h, { z0.h }, z0[0]
.arch armv9-a+sme-lutv2
.arch armv9-a+nosme-lutv2
luti4 { z0.b - z3.b }, zt0, { z0, z1 }
// CHECK: error: instruction requires: sme2 sme-lutv2
// CHECK: error: instruction requires: sme-lutv2
// CHECK: luti4 { z0.b - z3.b }, zt0, { z0, z1 }
16 changes: 8 additions & 8 deletions llvm/test/MC/AArch64/FP8_SME2/lut.s
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@@ -1,33 +1,33 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme2p1,+sme-lutv2 < %s \
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-lutv2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST

// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR

// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme2p1,+sme-lutv2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2,+sme2p1,+sme-lutv2 --no-print-imm-hex - \
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-lutv2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1,+sme-lutv2 --no-print-imm-hex - \
// RUN: | FileCheck %s --check-prefix=CHECK-INST

// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme2p1,+sme-lutv2 < %s \
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-lutv2 < %s \
// RUN: | llvm-objdump -d --mattr=-sme-lutv2 --no-print-imm-hex - \
// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN

// Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme2p1,+sme-lutv2 < %s \
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-lutv2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+sme2p1,+sme-lutv2 -disassemble -show-encoding \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-lutv2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST

luti4 {z0.b-z3.b}, zt0, {z0-z1} // 11000000-10001011-00000000-00000000
// CHECK-INST: luti4 { z0.b - z3.b }, zt0, { z0, z1 }
// CHECK-ENCODING: [0x00,0x00,0x8b,0xc0]
// CHECK-ERROR: instruction requires: sme2 sme-lutv2
// CHECK-ERROR: instruction requires: sme-lutv2
// CHECK-UNKNOWN: c08b0000 <unknown>

luti4 {z28.b-z31.b}, zt0, {z30-z31} // 11000000-10001011-00000011-11011100
// CHECK-INST: luti4 { z28.b - z31.b }, zt0, { z30, z31 }
// CHECK-ENCODING: [0xdc,0x03,0x8b,0xc0]
// CHECK-ERROR: instruction requires: sme2 sme-lutv2
// CHECK-ERROR: instruction requires: sme-lutv2
// CHECK-UNKNOWN: c08b03dc <unknown>

// Strided
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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/FP8_SME2/movt-diagnostics.s
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@@ -1,5 +1,5 @@

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-lutv2 2>&1 < %s | FileCheck %s
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-lutv2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector select register
movt z0, z31
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12 changes: 6 additions & 6 deletions llvm/test/MC/AArch64/FP8_SME2/movt.s
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@@ -1,14 +1,14 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-lutv2 < %s \
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-lutv2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST

// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR

// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-lutv2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2,+sme-lutv2 --no-print-imm-hex - \
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-lutv2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme-lutv2 --no-print-imm-hex - \
// RUN: | FileCheck %s --check-prefix=CHECK-INST

// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-lutv2 < %s \
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-lutv2 < %s \
// RUN: | llvm-objdump -d --mattr=-sme-lutv2 --no-print-imm-hex - \
// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN

Expand All @@ -21,11 +21,11 @@
movt zt0, z0 // 11000000-01001111-00000011-11100000
// CHECK-INST: movt zt0, z0
// CHECK-ENCODING: [0xe0,0x03,0x4f,0xc0]
// CHECK-ERROR: instruction requires: sme2 sme-lutv2
// CHECK-ERROR: instruction requires: sme-lutv2
// CHECK-UNKNOWN: c04f03e0 <unknown>

movt zt0[3, mul vl], z31 // 11000000-01001111-00110011-11111111
// CHECK-INST: movt zt0[3, mul vl], z31
// CHECK-ENCODING: [0xff,0x33,0x4f,0xc0]
// CHECK-ERROR: instruction requires: sme2 sme-lutv2
// CHECK-ERROR: instruction requires: sme-lutv2
// CHECK-UNKNOWN: c04f33ff <unknown>
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