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lattnerlattner
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split out an encoder for memri operands, allowing a relocation to be plopped
into the immediate field. This allows us to encode stuff like this: lbz r3, lo16(__ZL4init)(r4) ; globalopt.cpp:5 ; encoding: [0x88,0x64,A,A] ; fixup A - offset: 0, value: lo16(__ZL4init), kind: fixup_ppc_lo16 stw r3, lo16(__ZL1s)(r5) ; globalopt.cpp:6 ; encoding: [0x90,0x65,A,A] ; fixup A - offset: 0, value: lo16(__ZL1s), kind: fixup_ppc_lo16 With this, we should have a completely function MCCodeEmitter for PPC, wewt. llvm-svn: 119134
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-58
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5 files changed

+68
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‎llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp

Lines changed: 20 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,7 @@ namespace {
6666

6767
unsigned getHA16Encoding(const MachineInstr &MI, unsigned OpNo) const;
6868
unsigned getLO16Encoding(const MachineInstr &MI, unsigned OpNo) const;
69+
unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const;
6970
unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const;
7071

7172
const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
@@ -209,6 +210,22 @@ unsigned PPCCodeEmitter::getLO16Encoding(const MachineInstr &MI,
209210
return 0;
210211
}
211212

213+
unsigned PPCCodeEmitter::getMemRIEncoding(const MachineInstr &MI,
214+
unsigned OpNo) const {
215+
// Encode (imm, reg) as a memri, which has the low 16-bits as the
216+
// displacement and the next 5 bits as the register #.
217+
assert(MI.getOperand(OpNo+1).isReg());
218+
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 16;
219+
220+
const MachineOperand &MO = MI.getOperand(OpNo);
221+
if (MO.isImm())
222+
return (getMachineOpValue(MI, MO) & 0xFFFF) | RegBits;
223+
224+
// Add a fixup for the displacement field.
225+
MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low));
226+
return RegBits;
227+
}
228+
212229
unsigned PPCCodeEmitter::getMemRIXEncoding(const MachineInstr &MI,
213230
unsigned OpNo) const {
214231
// Encode (imm, reg) as a memrix, which has the low 14-bits as the
@@ -233,49 +250,9 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
233250
return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
234251
}
235252

236-
if (MO.isImm())
237-
return MO.getImm();
238-
239-
if (MO.isGlobal() || MO.isSymbol() || MO.isCPI() || MO.isJTI()) {
240-
unsigned Reloc = 0;
241-
assert((TM.getRelocationModel() != Reloc::PIC_ || MovePCtoLROffset) &&
242-
"MovePCtoLR not seen yet?");
243-
switch (MI.getOpcode()) {
244-
default: MI.dump(); llvm_unreachable("Unknown instruction for relocation!");
245-
// Loads.
246-
case PPC::LBZ:
247-
case PPC::LBZ8:
248-
case PPC::LHA:
249-
case PPC::LHA8:
250-
case PPC::LHZ:
251-
case PPC::LHZ8:
252-
case PPC::LWZ:
253-
case PPC::LWZ8:
254-
case PPC::LFS:
255-
case PPC::LFD:
256-
257-
// Stores.
258-
case PPC::STB:
259-
case PPC::STB8:
260-
case PPC::STH:
261-
case PPC::STH8:
262-
case PPC::STW:
263-
case PPC::STW8:
264-
case PPC::STFS:
265-
case PPC::STFD:
266-
Reloc = PPC::reloc_absolute_low;
267-
break;
268-
}
269-
270-
MCE.addRelocation(GetRelocation(MO, Reloc));
271-
} else {
272-
#ifndef NDEBUG
273-
errs() << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
274-
#endif
275-
llvm_unreachable(0);
276-
}
277-
278-
return 0;
253+
assert(MO.isImm() &&
254+
"Relocation required in an instruction that we cannot encode!");
255+
return MO.getImm();
279256
}
280257

281258
#include "PPCGenCodeEmitter.inc"

‎llvm/lib/Target/PowerPC/PPCInstr64Bit.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -493,7 +493,7 @@ def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
493493

494494
// Update forms.
495495
let mayLoad = 1 in
496-
def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
496+
def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
497497
ptr_rc:$rA),
498498
"lhau $rD, $disp($rA)", LdStGeneral,
499499
[]>, RegConstraint<"$rA = $ea_result">,
@@ -614,14 +614,14 @@ def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
614614

615615
let PPC970_Unit = 2 in {
616616

617-
def STBU8 : DForm_1<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
617+
def STBU8 : DForm_1a<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
618618
symbolLo:$ptroff, ptr_rc:$ptrreg),
619619
"stbu $rS, $ptroff($ptrreg)", LdStGeneral,
620620
[(set ptr_rc:$ea_res,
621621
(pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
622622
iaddroff:$ptroff))]>,
623623
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
624-
def STHU8 : DForm_1<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
624+
def STHU8 : DForm_1a<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
625625
symbolLo:$ptroff, ptr_rc:$ptrreg),
626626
"sthu $rS, $ptroff($ptrreg)", LdStGeneral,
627627
[(set ptr_rc:$ea_res,

‎llvm/lib/Target/PowerPC/PPCInstrFormats.td

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -102,6 +102,19 @@ class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
102102
InstrItinClass itin, list<dag> pattern>
103103
: I<opcode, OOL, IOL, asmstr, itin> {
104104
bits<5> A;
105+
bits<21> Addr;
106+
107+
let Pattern = pattern;
108+
109+
let Inst{6-10} = A;
110+
let Inst{11-15} = Addr{20-16}; // Base Reg
111+
let Inst{16-31} = Addr{15-0}; // Displacement
112+
}
113+
114+
class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
115+
InstrItinClass itin, list<dag> pattern>
116+
: I<opcode, OOL, IOL, asmstr, itin> {
117+
bits<5> A;
105118
bits<16> C;
106119
bits<5> B;
107120

@@ -112,6 +125,7 @@ class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
112125
let Inst{16-31} = C;
113126
}
114127

128+
115129
class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
116130
InstrItinClass itin, list<dag> pattern>
117131
: DForm_base<opcode, OOL, IOL, asmstr, itin, pattern>;
@@ -147,8 +161,7 @@ class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
147161
InstrItinClass itin, list<dag> pattern>
148162
: DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
149163
let A = 0;
150-
let B = 0;
151-
let C = 0;
164+
let Addr = 0;
152165
}
153166

154167
class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -316,6 +316,7 @@ def crbitm: Operand<i8> {
316316
def memri : Operand<iPTR> {
317317
let PrintMethod = "printMemRegImm";
318318
let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
319+
let EncoderMethod = "getMemRIEncoding";
319320
}
320321
def memrr : Operand<iPTR> {
321322
let PrintMethod = "printMemRegReg";
@@ -763,33 +764,33 @@ def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
763764

764765
// Unindexed (r+i) Stores with Update (preinc).
765766
let PPC970_Unit = 2 in {
766-
def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
767+
def STBU : DForm_1a<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
767768
symbolLo:$ptroff, ptr_rc:$ptrreg),
768769
"stbu $rS, $ptroff($ptrreg)", LdStGeneral,
769770
[(set ptr_rc:$ea_res,
770771
(pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
771772
iaddroff:$ptroff))]>,
772773
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
773-
def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
774+
def STHU : DForm_1a<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
774775
symbolLo:$ptroff, ptr_rc:$ptrreg),
775776
"sthu $rS, $ptroff($ptrreg)", LdStGeneral,
776777
[(set ptr_rc:$ea_res,
777778
(pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
778779
iaddroff:$ptroff))]>,
779780
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
780-
def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
781+
def STWU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
781782
symbolLo:$ptroff, ptr_rc:$ptrreg),
782783
"stwu $rS, $ptroff($ptrreg)", LdStGeneral,
783784
[(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
784785
iaddroff:$ptroff))]>,
785786
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
786-
def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
787+
def STFSU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
787788
symbolLo:$ptroff, ptr_rc:$ptrreg),
788789
"stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
789790
[(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
790791
iaddroff:$ptroff))]>,
791792
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
792-
def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
793+
def STFDU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
793794
symbolLo:$ptroff, ptr_rc:$ptrreg),
794795
"stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
795796
[(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,

‎llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp

Lines changed: 24 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,8 @@ class PPCMCCodeEmitter : public MCCodeEmitter {
6666
SmallVectorImpl<MCFixup> &Fixups) const;
6767
unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
6868
SmallVectorImpl<MCFixup> &Fixups) const;
69+
unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
70+
SmallVectorImpl<MCFixup> &Fixups) const;
6971
unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
7072
SmallVectorImpl<MCFixup> &Fixups) const;
7173
unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
@@ -147,10 +149,29 @@ unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
147149
return 0;
148150
}
149151

152+
unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
153+
SmallVectorImpl<MCFixup> &Fixups) const {
154+
// Encode (imm, reg) as a memri, which has the low 16-bits as the
155+
// displacement and the next 5 bits as the register #.
156+
assert(MI.getOperand(OpNo+1).isReg());
157+
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
158+
159+
const MCOperand &MO = MI.getOperand(OpNo);
160+
if (MO.isImm())
161+
return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
162+
163+
// Add a fixup for the displacement field.
164+
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
165+
(MCFixupKind)PPC::fixup_ppc_lo16));
166+
return RegBits;
167+
}
168+
169+
150170
unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
151171
SmallVectorImpl<MCFixup> &Fixups) const {
152172
// Encode (imm, reg) as a memrix, which has the low 14-bits as the
153173
// displacement and the next 5 bits as the register #.
174+
assert(MI.getOperand(OpNo+1).isReg());
154175
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
155176

156177
const MCOperand &MO = MI.getOperand(OpNo);
@@ -182,11 +203,9 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
182203
return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
183204
}
184205

185-
if (MO.isImm())
186-
return MO.getImm();
187-
188-
// FIXME.
189-
return 0;
206+
assert(MO.isImm() &&
207+
"Relocation required in an instruction that we cannot encode!");
208+
return MO.getImm();
190209
}
191210

192211

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