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review comments:
 - switch to wave_readlaneat to follow llvm naming conventions
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9 files changed

+32
-32
lines changed

9 files changed

+32
-32
lines changed

‎clang/lib/CodeGen/CGBuiltin.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18851,7 +18851,7 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
1885118851
return EmitRuntimeCall(CGM.CreateRuntimeFunction(FT, Name, {},
1885218852
/*Local=*/false,
1885318853
/*AssumeConvergent=*/true),
18854-
ArrayRef{OpExpr, OpIndex}, "hlsl.waveReadLaneAt");
18854+
ArrayRef{OpExpr, OpIndex}, "hlsl.wave.readlaneAt");
1885518855
}
1885618856
case Builtin::BI__builtin_hlsl_elementwise_sign: {
1885718857
Value *Op0 = EmitScalarExpr(E->getArg(0));

‎clang/lib/CodeGen/CGHLSLRuntime.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,7 @@ class CGHLSLRuntime {
8787
GENERATE_HLSL_INTRINSIC_FUNCTION(SDot, sdot)
8888
GENERATE_HLSL_INTRINSIC_FUNCTION(UDot, udot)
8989
GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane)
90-
GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, waveReadLaneAt)
90+
GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, wave_readlaneat)
9191

9292
//===----------------------------------------------------------------------===//
9393
// End of reserved area for HLSL intrinsic getters.

‎clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -10,27 +10,27 @@
1010
// CHECK-LABEL: test_int
1111
int test_int(int expr, uint idx) {
1212
// CHECK-SPIRV: %[[#entry_tok:]] = call token @llvm.experimental.convergence.entry()
13-
// CHECK-SPIRV: %[[RET:.*]] = call [[TY:.*]] @llvm.spv.waveReadLaneAt.i32([[TY]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok]]) ]
14-
// CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.waveReadLaneAt.i32([[TY]] %[[#]], i32 %[[#]])
13+
// CHECK-SPIRV: %[[RET:.*]] = call [[TY:.*]] @llvm.spv.wave.readlaneat.i32([[TY]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok]]) ]
14+
// CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.readlaneat.i32([[TY]] %[[#]], i32 %[[#]])
1515
// CHECK: ret [[TY]] %[[RET]]
1616
return WaveReadLaneAt(expr, idx);
1717
}
1818

19-
// CHECK-DXIL: declare [[TY]] @llvm.dx.waveReadLaneAt.i32([[TY]], i32) #[[#attr:]]
20-
// CHECK-SPIRV: declare [[TY]] @llvm.spv.waveReadLaneAt.i32([[TY]], i32) #[[#attr:]]
19+
// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.readlaneat.i32([[TY]], i32) #[[#attr:]]
20+
// CHECK-SPIRV: declare [[TY]] @llvm.spv.wave.readlaneat.i32([[TY]], i32) #[[#attr:]]
2121

2222
// Test basic lowering to runtime function call with array and float value.
2323

2424
// CHECK-LABEL: test_floatv4
2525
float4 test_floatv4(float4 expr, uint idx) {
2626
// CHECK-SPIRV: %[[#entry_tok1:]] = call token @llvm.experimental.convergence.entry()
27-
// CHECK-SPIRV: %[[RET1:.*]] = call [[TY1:.*]] @llvm.spv.waveReadLaneAt.v4f32([[TY1]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok1]]) ]
28-
// CHECK-DXIL: %[[RET1:.*]] = call [[TY1:.*]] @llvm.dx.waveReadLaneAt.v4f32([[TY1]] %[[#]], i32 %[[#]])
27+
// CHECK-SPIRV: %[[RET1:.*]] = call [[TY1:.*]] @llvm.spv.wave.readlaneat.v4f32([[TY1]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok1]]) ]
28+
// CHECK-DXIL: %[[RET1:.*]] = call [[TY1:.*]] @llvm.dx.wave.readlaneat.v4f32([[TY1]] %[[#]], i32 %[[#]])
2929
// CHECK: ret [[TY1]] %[[RET1]]
3030
return WaveReadLaneAt(expr, idx);
3131
}
3232

33-
// CHECK-DXIL: declare [[TY1]] @llvm.dx.waveReadLaneAt.v4f32([[TY1]], i32) #[[#attr]]
34-
// CHECK-SPIRV: declare [[TY1]] @llvm.spv.waveReadLaneAt.v4f32([[TY1]], i32) #[[#attr]]
33+
// CHECK-DXIL: declare [[TY1]] @llvm.dx.wave.readlaneat.v4f32([[TY1]], i32) #[[#attr]]
34+
// CHECK-SPIRV: declare [[TY1]] @llvm.spv.wave.readlaneat.v4f32([[TY1]], i32) #[[#attr]]
3535

3636
// CHECK: attributes #[[#attr]] = {{{.*}} convergent {{.*}}}

‎llvm/include/llvm/IR/IntrinsicsDirectX.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLV
8383
def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>;
8484
def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
8585
def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
86-
def int_dx_waveReadLaneAt : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>;
86+
def int_dx_wave_readlaneat : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>;
8787
def int_dx_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>;
8888
def int_dx_step : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty, LLVMMatchType<0>], [IntrNoMem]>;
8989
}

‎llvm/include/llvm/IR/IntrinsicsSPIRV.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,6 @@ let TargetPrefix = "spv" in {
8282
[llvm_anyint_ty, LLVMScalarOrSameVectorWidth<0, LLVMVectorElementType<0>>],
8383
[IntrNoMem, Commutative] >;
8484
def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
85-
def int_spv_waveReadLaneAt : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>;
85+
def int_spv_wave_readlaneat : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>;
8686
def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty]>;
8787
}

‎llvm/lib/Target/DirectX/DXIL.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -804,7 +804,7 @@ def WaveIsFirstLane : DXILOp<110, waveIsFirstLane> {
804804

805805
def WaveReadLaneAt: DXILOp<117, waveReadLaneAt> {
806806
let Doc = "returns the value from the specified lane";
807-
let LLVMIntrinsic = int_dx_waveReadLaneAt;
807+
let LLVMIntrinsic = int_dx_wave_readlaneat;
808808
let arguments = [OverloadTy, Int32Ty];
809809
let result = OverloadTy;
810810
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy, DoubleTy, Int1Ty, Int16Ty, Int32Ty]>];

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2677,7 +2677,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
26772677
.addUse(GR.getSPIRVTypeID(ResType))
26782678
.addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
26792679
}
2680-
case Intrinsic::spv_waveReadLaneAt:
2680+
case Intrinsic::spv_wave_readlaneat:
26812681
return selectWaveReadLaneAt(ResVReg, ResType, I);
26822682
case Intrinsic::spv_step:
26832683
return selectStep(ResVReg, ResType, I);

‎llvm/test/CodeGen/DirectX/WaveReadLaneAt.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -5,49 +5,49 @@
55
define noundef half @wave_rla_half(half noundef %expr, i32 noundef %idx) {
66
entry:
77
; CHECK: call half @dx.op.waveReadLaneAt.f16(i32 117, half %expr, i32 %idx)
8-
%ret = call half @llvm.dx.waveReadLaneAt.f16(half %expr, i32 %idx)
8+
%ret = call half @llvm.dx.wave.readlaneat.f16(half %expr, i32 %idx)
99
ret half %ret
1010
}
1111

1212
define noundef float @wave_rla_float(float noundef %expr, i32 noundef %idx) {
1313
entry:
1414
; CHECK: call float @dx.op.waveReadLaneAt.f32(i32 117, float %expr, i32 %idx)
15-
%ret = call float @llvm.dx.waveReadLaneAt(float %expr, i32 %idx)
15+
%ret = call float @llvm.dx.wave.readlaneat(float %expr, i32 %idx)
1616
ret float %ret
1717
}
1818

1919
define noundef double @wave_rla_double(double noundef %expr, i32 noundef %idx) {
2020
entry:
2121
; CHECK: call double @dx.op.waveReadLaneAt.f64(i32 117, double %expr, i32 %idx)
22-
%ret = call double @llvm.dx.waveReadLaneAt(double %expr, i32 %idx)
22+
%ret = call double @llvm.dx.wave.readlaneat(double %expr, i32 %idx)
2323
ret double %ret
2424
}
2525

2626
define noundef i1 @wave_rla_i1(i1 noundef %expr, i32 noundef %idx) {
2727
entry:
2828
; CHECK: call i1 @dx.op.waveReadLaneAt.i1(i32 117, i1 %expr, i32 %idx)
29-
%ret = call i1 @llvm.dx.waveReadLaneAt.i1(i1 %expr, i32 %idx)
29+
%ret = call i1 @llvm.dx.wave.readlaneat.i1(i1 %expr, i32 %idx)
3030
ret i1 %ret
3131
}
3232

3333
define noundef i16 @wave_rla_i16(i16 noundef %expr, i32 noundef %idx) {
3434
entry:
3535
; CHECK: call i16 @dx.op.waveReadLaneAt.i16(i32 117, i16 %expr, i32 %idx)
36-
%ret = call i16 @llvm.dx.waveReadLaneAt.i16(i16 %expr, i32 %idx)
36+
%ret = call i16 @llvm.dx.wave.readlaneat.i16(i16 %expr, i32 %idx)
3737
ret i16 %ret
3838
}
3939

4040
define noundef i32 @wave_rla_i32(i32 noundef %expr, i32 noundef %idx) {
4141
entry:
4242
; CHECK: call i32 @dx.op.waveReadLaneAt.i32(i32 117, i32 %expr, i32 %idx)
43-
%ret = call i32 @llvm.dx.waveReadLaneAt.i32(i32 %expr, i32 %idx)
43+
%ret = call i32 @llvm.dx.wave.readlaneat.i32(i32 %expr, i32 %idx)
4444
ret i32 %ret
4545
}
4646

47-
declare half @llvm.dx.waveReadLaneAt.f16(half, i32)
48-
declare float @llvm.dx.waveReadLaneAt.f32(float, i32)
49-
declare double @llvm.dx.waveReadLaneAt.f64(double, i32)
47+
declare half @llvm.dx.wave.readlaneat.f16(half, i32)
48+
declare float @llvm.dx.wave.readlaneat.f32(float, i32)
49+
declare double @llvm.dx.wave.readlaneat.f64(double, i32)
5050

51-
declare i1 @llvm.dx.waveReadLaneAt.i1(i1, i32)
52-
declare i16 @llvm.dx.waveReadLaneAt.i16(i16, i32)
53-
declare i32 @llvm.dx.waveReadLaneAt.i32(i32, i32)
51+
declare i1 @llvm.dx.wave.readlaneat.i1(i1, i32)
52+
declare i16 @llvm.dx.wave.readlaneat.i16(i16, i32)
53+
declare i32 @llvm.dx.wave.readlaneat.i32(i32, i32)

‎llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
define float @test_1(float %fexpr, i32 %idx) {
1515
entry:
1616
; CHECK: %[[#fret:]] = OpGroupNonUniformShuffle %[[#f32]] %[[#fexpr]] %[[#idx1]] %[[#scope]]
17-
%0 = call float @llvm.spv.waveReadLaneAt.f32(float %fexpr, i32 %idx)
17+
%0 = call float @llvm.spv.wave.readlaneat.f32(float %fexpr, i32 %idx)
1818
ret float %0
1919
}
2020

@@ -23,7 +23,7 @@ entry:
2323
define i32 @test_2(i32 %iexpr, i32 %idx) {
2424
entry:
2525
; CHECK: %[[#iret:]] = OpGroupNonUniformShuffle %[[#uint]] %[[#iexpr]] %[[#idx2]] %[[#scope]]
26-
%0 = call i32 @llvm.spv.waveReadLaneAt.i32(i32 %iexpr, i32 %idx)
26+
%0 = call i32 @llvm.spv.wave.readlaneat.i32(i32 %iexpr, i32 %idx)
2727
ret i32 %0
2828
}
2929

@@ -32,10 +32,10 @@ entry:
3232
define <4 x i1> @test_3(<4 x i1> %vbexpr, i32 %idx) {
3333
entry:
3434
; CHECK: %[[#vbret:]] = OpGroupNonUniformShuffle %[[#v4_bool]] %[[#vbexpr]] %[[#idx3]] %[[#scope]]
35-
%0 = call <4 x i1> @llvm.spv.waveReadLaneAt.v4i1(<4 x i1> %vbexpr, i32 %idx)
35+
%0 = call <4 x i1> @llvm.spv.wave.readlaneat.v4i1(<4 x i1> %vbexpr, i32 %idx)
3636
ret <4 x i1> %0
3737
}
3838

39-
declare float @llvm.spv.waveReadLaneAt.f32(float, i32)
40-
declare i32 @llvm.spv.waveReadLaneAt.i32(i32, i32)
41-
declare <4 x i1> @llvm.spv.waveReadLaneAt.v4i1(<4 x i1>, i32)
39+
declare float @llvm.spv.wave.readlaneat.f32(float, i32)
40+
declare i32 @llvm.spv.wave.readlaneat.i32(i32, i32)
41+
declare <4 x i1> @llvm.spv.wave.readlaneat.v4i1(<4 x i1>, i32)

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