Skip to content

Commit f438815

Browse files
committed
fixup! Remove Latency=2
1 parent 1e61a62 commit f438815

File tree

1 file changed

+0
-2
lines changed

1 file changed

+0
-2
lines changed

llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -125,10 +125,8 @@ def : WriteRes<WriteCSR, [p8700ALQ]>;
125125

126126
// Handle CTI Pipeline.
127127
def : WriteRes<WriteJmp, [p8700IssueCTI]>;
128-
let Latency = 2 in {
129128
def : WriteRes<WriteJal, [p8700IssueCTI]>;
130129
def : WriteRes<WriteJalr, [p8700IssueCTI]>;
131-
}
132130

133131
// Handle FPU Pipelines.
134132
def p8700FPQ : ProcResource<3> { let BufferSize = 16; }

0 commit comments

Comments
 (0)