resolve comment

Author: XinWang10

llvm/lib/Target/X86/X86InstrMisc.td

@@ -229,7 +229,7 @@ def PUSHA16  : I<0x60, RawFrm, (outs), (ins), "pushaw", []>,
                OpSize16, Requires<[Not64BitMode]>;
 }
 
-let Constraints = "$src = $dst", SchedRW = [WriteBSWAP32], Predicates = [NoEGPR] in {
+let Constraints = "$src = $dst", SchedRW = [WriteBSWAP32], Predicates = [NoNDD] in {
 // This instruction is a consequence of BSWAP32r observing operand size. The
 // encoding is valid, but the behavior is undefined.
 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
@@ -1150,30 +1150,31 @@ let Predicates = [HasMOVBE, HasEGPR, In64BitMode] in {
                          [(store (bswap GR64:$src), addr:$dst)]>,
                        EVEX, NoCD8, T_MAP4;
   }
-  let SchedRW = [WriteALU] in {
-  def MOVBE16rr_EVEX : I<0x61, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
-                         "movbe{w}\t{$src, $dst|$dst, $src}", 
-                         [(set GR16:$dst, (bswap GR16:$src))]>,
-                       EVEX, NoCD8, T_MAP4, PD;
-  def MOVBE32rr_EVEX : I<0x61, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
-                         "movbe{l}\t{$src, $dst|$dst, $src}", 
-                         [(set GR32:$dst, (bswap GR32:$src))]>,
-                       EVEX, NoCD8, T_MAP4;
-  def MOVBE64rr_EVEX : RI<0x61, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
-                          "movbe{q}\t{$src, $dst|$dst, $src}", 
-                          [(set GR64:$dst, (bswap GR64:$src))]>,
-                       EVEX, NoCD8, T_MAP4;
+}
 
-  def MOVBE16rr_EVEX_REV : I<0x60, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
-                             "movbe{w}\t{$src, $dst|$dst, $src}", []>,
-                           EVEX, NoCD8, T_MAP4, PD;
-  def MOVBE32rr_EVEX_REV : I<0x60, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
-                             "movbe{l}\t{$src, $dst|$dst, $src}", []>,
-                           EVEX, NoCD8, T_MAP4;
-  def MOVBE64rr_EVEX_REV : RI<0x60, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
-                              "movbe{q}\t{$src, $dst|$dst, $src}", []>,
-                           EVEX, NoCD8, T_MAP4;
-  }
+let SchedRW = [WriteALU], Predicates = [HasMOVBE, HasNDD, In64BitMode] in {
+def MOVBE16rr_EVEX : I<0x61, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
+                        "movbe{w}\t{$src, $dst|$dst, $src}",
+                        [(set GR16:$dst, (bswap GR16:$src))]>,
+                      EVEX, NoCD8, T_MAP4, PD;
+def MOVBE32rr_EVEX : I<0x61, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
+                        "movbe{l}\t{$src, $dst|$dst, $src}",
+                        [(set GR32:$dst, (bswap GR32:$src))]>,
+                      EVEX, NoCD8, T_MAP4;
+def MOVBE64rr_EVEX : RI<0x61, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
+                        "movbe{q}\t{$src, $dst|$dst, $src}",
+                        [(set GR64:$dst, (bswap GR64:$src))]>,
+                      EVEX, NoCD8, T_MAP4;
+
+def MOVBE16rr_EVEX_REV : I<0x60, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
+                            "movbe{w}\t{$src, $dst|$dst, $src}", []>,
+                          EVEX, NoCD8, T_MAP4, PD;
+def MOVBE32rr_EVEX_REV : I<0x60, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
+                            "movbe{l}\t{$src, $dst|$dst, $src}", []>,
+                          EVEX, NoCD8, T_MAP4;
+def MOVBE64rr_EVEX_REV : RI<0x60, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
+                            "movbe{q}\t{$src, $dst|$dst, $src}", []>,
+                          EVEX, NoCD8, T_MAP4;
 }
 
 //===----------------------------------------------------------------------===//

llvm/test/CodeGen/X86/movbe.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
 ; RUN: llc -mtriple=x86_64-linux -mcpu=atom < %s | FileCheck %s
 ; RUN: llc -mtriple=x86_64-linux -mcpu=slm < %s | FileCheck %s -check-prefix=SLM
-; RUN: llc -mtriple=x86_64-linux -mcpu=slm -mattr=+egpr --show-mc-encoding < %s | FileCheck %s -check-prefix=EGPR
+; RUN: llc -mtriple=x86_64-linux -mcpu=slm -mattr=+egpr,+ndd --show-mc-encoding < %s | FileCheck %s -check-prefix=EGPR
 
 declare i16 @llvm.bswap.i16(i16) nounwind readnone
 declare i32 @llvm.bswap.i32(i32) nounwind readnone