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replace bitwise operators for boolean comparisons
1 parent 742c808 commit fc25a1f

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1 file changed

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llvm/lib/Target/AMDGPU/SIInstrInfo.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -716,25 +716,25 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
716716
static bool isVGPRSpill(const MachineInstr &MI) {
717717
return MI.getOpcode() != AMDGPU::SI_SPILL_S32_TO_VGPR &&
718718
MI.getOpcode() != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
719-
(isSpill(MI) & isVALU(MI));
719+
(isSpill(MI) && isVALU(MI));
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}
721721

722722
bool isVGPRSpill(uint16_t Opcode) const {
723723
return Opcode != AMDGPU::SI_SPILL_S32_TO_VGPR &&
724724
Opcode != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
725-
(isSpill(Opcode) & isVALU(Opcode));
725+
(isSpill(Opcode) && isVALU(Opcode));
726726
}
727727

728728
static bool isSGPRSpill(const MachineInstr &MI) {
729729
return MI.getOpcode() == AMDGPU::SI_SPILL_S32_TO_VGPR ||
730730
MI.getOpcode() == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
731-
(isSpill(MI) & isSALU(MI));
731+
(isSpill(MI) && isSALU(MI));
732732
}
733733

734734
bool isSGPRSpill(uint16_t Opcode) const {
735735
return Opcode == AMDGPU::SI_SPILL_S32_TO_VGPR ||
736736
Opcode == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
737-
(isSpill(Opcode) & isSALU(Opcode));
737+
(isSpill(Opcode) && isSALU(Opcode));
738738
}
739739

740740
bool isSpill(uint16_t Opcode) const {

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