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SamTebbs33SamTebbs33
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fixup: add decode function
1 parent c8a6a5d commit fc6be26

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4 files changed

+25
-10
lines changed

4 files changed

+25
-10
lines changed

‎llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -143,6 +143,9 @@ DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
143143
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
144144
uint64_t Address,
145145
const MCDisassembler *Decoder);
146+
static DecodeStatus DecodePPRorPNRRegisterClass(MCInst &Inst, unsigned RegNo,
147+
uint64_t Addr,
148+
const MCDisassembler *Decoder);
146149
static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo,
147150
uint64_t Address,
148151
const MCDisassembler *Decoder);
@@ -741,6 +744,18 @@ static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
741744
return Success;
742745
}
743746

747+
static DecodeStatus DecodePPRorPNRRegisterClass(MCInst &Inst, unsigned RegNo,
748+
uint64_t Addr,
749+
const MCDisassembler *Decoder) {
750+
if (RegNo > 15)
751+
return Fail;
752+
753+
unsigned Register =
754+
AArch64MCRegisterClasses[AArch64::PPRorPNRRegClassID].getRegister(RegNo);
755+
Inst.addOperand(MCOperand::createReg(Register));
756+
return Success;
757+
}
758+
744759
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
745760
uint64_t Addr,
746761
const MCDisassembler *Decoder) {

‎llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -57,11 +57,11 @@ tracksRegLiveness: true
5757
body: |
5858
bb.1:
5959
; CHECK-LABEL: name: inlineasm_virt_reg_output
60-
; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1310730 /* regdef:PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15 */, def %0
60+
; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0
6161
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
6262
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
6363
; CHECK-NEXT: RET_ReallyLR implicit $w0
64-
INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1310730 /* regdef:GPR32common */, def %0:gpr32common
64+
INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0:gpr32common
6565
%1:_(s32) = COPY %0
6666
$w0 = COPY %1(s32)
6767
RET_ReallyLR implicit $w0
@@ -75,12 +75,12 @@ tracksRegLiveness: true
7575
body: |
7676
bb.1:
7777
; CHECK-LABEL: name: inlineasm_virt_mixed_types
78-
; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1310730 /* regdef:PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15 */, def %0, 2162698 /* regdef:WSeqPairsClass */, def %1
78+
; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, {{[0-9]+}} /* regdef:FPR64 */, def %1
7979
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
8080
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY %1
8181
; CHECK-NEXT: $d0 = COPY [[COPY1]](s64)
8282
; CHECK-NEXT: RET_ReallyLR implicit $d0
83-
INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1310730 /* regdef:GPR32common */, def %0:gpr32common, 2162698 /* regdef:FPR64 */, def %1:fpr64
83+
INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0:gpr32common, 2621450 /* regdef:FPR64 */, def %1:fpr64
8484
%3:_(s32) = COPY %0
8585
%4:_(s64) = COPY %1
8686
$d0 = COPY %4(s64)

‎llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -91,10 +91,10 @@ body: |
9191
; CHECK-NEXT: {{ $}}
9292
; CHECK-NEXT: [[LOADgot:%[0-9]+]]:gpr64common = LOADgot target-flags(aarch64-got) @c
9393
; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c)
94-
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 */, def %2, 2147483657 /* reguse tiedto:$0 */, [[LDRDui]](tied-def 3)
94+
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, [[LDRDui]](tied-def 3)
9595
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY %2
9696
; CHECK-NEXT: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c)
97-
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[LDRDui1]](tied-def 3)
97+
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[LDRDui1]](tied-def 3)
9898
; CHECK-NEXT: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr %2
9999
; CHECK-NEXT: nofpexcept FCMPDrr %4, killed [[FNEGDr]], implicit-def $nzcv, implicit $fpcr
100100
; CHECK-NEXT: Bcc 1, %bb.2, implicit $nzcv
@@ -111,10 +111,10 @@ body: |
111111
112112
%6:gpr64common = LOADgot target-flags(aarch64-got) @c
113113
%3:fpr64 = LDRDui %6, 0 :: (dereferenceable load (s64) from @c)
114-
INLINEASM &"", 1 /* sideeffect attdialect */, 2359306 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, %3(tied-def 3)
114+
INLINEASM &"", 1 /* sideeffect attdialect */, 2621450 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, %3(tied-def 3)
115115
%0:fpr64 = COPY %2
116116
%5:fpr64 = LDRDui %6, 0 :: (dereferenceable load (s64) from @c)
117-
INLINEASM &"", 1 /* sideeffect attdialect */, 2359306 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, %5(tied-def 3)
117+
INLINEASM &"", 1 /* sideeffect attdialect */, 2621450 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, %5(tied-def 3)
118118
%7:fpr64 = FNEGDr %2
119119
nofpexcept FCMPDrr %4, killed %7, implicit-def $nzcv, implicit $fpcr
120120
Bcc 1, %bb.2, implicit $nzcv

‎llvm/test/CodeGen/AArch64/peephole-insvigpr.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -487,7 +487,7 @@ body: |
487487
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
488488
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
489489
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[DEF]]
490-
; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, {{[0-9]+}} /* regdef:WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 */, def %1, 262158 /* mem:m */, killed [[COPY1]]
490+
; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, {{[0-9]+}} /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed [[COPY1]]
491491
; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
492492
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub
493493
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
@@ -505,7 +505,7 @@ body: |
505505
%0:gpr64common = COPY $x0
506506
%2:gpr64all = IMPLICIT_DEF
507507
%3:gpr64sp = COPY %2
508-
INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 2359306 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed %3
508+
INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 2621450 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed %3
509509
%4:fpr128 = MOVIv2d_ns 0
510510
%5:fpr64 = COPY %4.dsub
511511
%7:fpr128 = IMPLICIT_DEF

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