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[RISCV] Implement Clang Builtins for XCValu Extension in CV32E40P #100684
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2ea18ad
[RISCV] Implement Clang Builtins for XCValu Extension in CV32E40P
realqhc ec017e3
Declare builtins to take MachineType
realqhc b8262f9
fix header location
realqhc 4115204
remove unnecessary cv.min/max, move XCV builtins into RISCV namespace
realqhc 9c3b354
fix wrongly referenced min/max in riscv_corev_alu.h, generate c-api t…
realqhc 1b56a7f
Generate extb[s/z], sle[u] by instruction. Remove no longer used intr…
realqhc 7ee760d
Remove unused intrinsics, fix sle[u] issue by zext instruction.
realqhc 71d2b92
Fix xcvalu-c-api, alphabetize cmake list
realqhc 3af76e2
Merge branch 'main' into alu-clang-builtins
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,41 @@ | ||
//==- BuiltinsRISCVXCV.td - RISC-V CORE-V Builtin database ----*- C++ -*-==// | ||
// | ||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||
// See https://llvm.org/LICENSE.txt for license information. | ||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
// | ||
//===----------------------------------------------------------------------===// | ||
// | ||
// This file defines the CORE-V-specific builtin function database. Users of | ||
// this file must define the BUILTIN macro to make use of this information. | ||
// | ||
//===----------------------------------------------------------------------===// | ||
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class RISCXCVBuiltin<string prototype, string features = ""> : TargetBuiltin { | ||
let Spellings = ["__builtin_riscv_cv_" # NAME]; | ||
let Prototype = prototype; | ||
let Features = features; | ||
} | ||
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let Attributes = [NoThrow, Const] in { | ||
//===----------------------------------------------------------------------===// | ||
// XCValu extension. | ||
//===----------------------------------------------------------------------===// | ||
def alu_slet : RISCXCVBuiltin<"int(int, int)", "xcvalu">; | ||
def alu_sletu : RISCXCVBuiltin<"int(unsigned int, unsigned int)", "xcvalu">; | ||
def alu_exths : RISCXCVBuiltin<"int(int)", "xcvalu">; | ||
def alu_exthz : RISCXCVBuiltin<"unsigned int(unsigned int)", "xcvalu">; | ||
def alu_extbs : RISCXCVBuiltin<"int(int)", "xcvalu">; | ||
def alu_extbz : RISCXCVBuiltin<"unsigned int(unsigned int)", "xcvalu">; | ||
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def alu_clip : RISCXCVBuiltin<"int(int, int)", "xcvalu">; | ||
def alu_clipu : RISCXCVBuiltin<"unsigned int(unsigned int, unsigned int)", "xcvalu">; | ||
def alu_addN : RISCXCVBuiltin<"int(int, int, unsigned int)", "xcvalu">; | ||
def alu_adduN : RISCXCVBuiltin<"unsigned int(unsigned int, unsigned int, unsigned int)", "xcvalu">; | ||
def alu_addRN : RISCXCVBuiltin<"int(int, int, unsigned int)", "xcvalu">; | ||
def alu_adduRN : RISCXCVBuiltin<"unsigned int(unsigned int, unsigned int, unsigned int)", "xcvalu">; | ||
def alu_subN : RISCXCVBuiltin<"int(int, int, unsigned int)", "xcvalu">; | ||
def alu_subuN : RISCXCVBuiltin<"unsigned int(unsigned int, unsigned int, unsigned int)", "xcvalu">; | ||
def alu_subRN : RISCXCVBuiltin<"int(int, int, unsigned int)", "xcvalu">; | ||
def alu_subuRN : RISCXCVBuiltin<"unsigned int(unsigned int, unsigned int, unsigned int)", "xcvalu">; | ||
} // Attributes = [NoThrow, Const] |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,128 @@ | ||
/*===---- riscv_corev_alu.h - CORE-V ALU intrinsics ------------------------=== | ||
* | ||
* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||
* See https://llvm.org/LICENSE.txt for license information. | ||
* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
* | ||
*===-----------------------------------------------------------------------=== | ||
*/ | ||
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#ifndef __RISCV_COREV_ALU_H | ||
#define __RISCV_COREV_ALU_H | ||
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#include <stdint.h> | ||
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#if defined(__cplusplus) | ||
extern "C" { | ||
#endif | ||
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#if defined(__riscv_xcvalu) | ||
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#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__)) | ||
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static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_abs(long a) { | ||
return __builtin_abs(a); | ||
} | ||
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static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_alu_slet(long a, long b) { | ||
return __builtin_riscv_cv_alu_slet(a, b); | ||
} | ||
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static __inline__ long __DEFAULT_FN_ATTRS | ||
__riscv_cv_alu_sletu(unsigned long a, unsigned long b) { | ||
return __builtin_riscv_cv_alu_sletu(a, b); | ||
} | ||
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static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_alu_min(long a, long b) { | ||
return __builtin_elementwise_min(a, b); | ||
} | ||
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static __inline__ unsigned long __DEFAULT_FN_ATTRS | ||
__riscv_cv_alu_minu(unsigned long a, unsigned long b) { | ||
return __builtin_elementwise_min(a, b); | ||
} | ||
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static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_alu_max(long a, long b) { | ||
return __builtin_elementwise_max(a, b); | ||
} | ||
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static __inline__ unsigned long __DEFAULT_FN_ATTRS | ||
__riscv_cv_alu_maxu(unsigned long a, unsigned long b) { | ||
return __builtin_elementwise_max(a, b); | ||
} | ||
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static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_alu_exths(int16_t a) { | ||
return __builtin_riscv_cv_alu_exths(a); | ||
} | ||
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static __inline__ unsigned long __DEFAULT_FN_ATTRS | ||
__riscv_cv_alu_exthz(uint16_t a) { | ||
return __builtin_riscv_cv_alu_exthz(a); | ||
} | ||
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static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_alu_extbs(int8_t a) { | ||
return __builtin_riscv_cv_alu_extbs(a); | ||
} | ||
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static __inline__ unsigned long __DEFAULT_FN_ATTRS | ||
__riscv_cv_alu_extbz(uint8_t a) { | ||
return __builtin_riscv_cv_alu_extbz(a); | ||
} | ||
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static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_alu_clip(long a, | ||
unsigned long b) { | ||
return __builtin_riscv_cv_alu_clip(a, b); | ||
} | ||
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static __inline__ unsigned long __DEFAULT_FN_ATTRS | ||
__riscv_cv_alu_clipu(unsigned long a, unsigned long b) { | ||
return __builtin_riscv_cv_alu_clipu(a, b); | ||
} | ||
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static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_alu_addN(long a, long b, | ||
uint8_t shft) { | ||
return __builtin_riscv_cv_alu_addN(a, b, shft); | ||
} | ||
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static __inline__ unsigned long __DEFAULT_FN_ATTRS | ||
__riscv_cv_alu_adduN(unsigned long a, unsigned long b, uint8_t shft) { | ||
return __builtin_riscv_cv_alu_adduN(a, b, shft); | ||
} | ||
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static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_alu_addRN(long a, long b, | ||
uint8_t shft) { | ||
return __builtin_riscv_cv_alu_addRN(a, b, shft); | ||
} | ||
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static __inline__ unsigned long __DEFAULT_FN_ATTRS | ||
__riscv_cv_alu_adduRN(unsigned long a, unsigned long b, uint8_t shft) { | ||
return __builtin_riscv_cv_alu_adduRN(a, b, shft); | ||
} | ||
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static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_alu_subN(long a, long b, | ||
uint8_t shft) { | ||
return __builtin_riscv_cv_alu_subN(a, b, shft); | ||
} | ||
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static __inline__ unsigned long __DEFAULT_FN_ATTRS | ||
__riscv_cv_alu_subuN(unsigned long a, unsigned long b, uint8_t shft) { | ||
return __builtin_riscv_cv_alu_subuN(a, b, shft); | ||
} | ||
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static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_alu_subRN(long a, long b, | ||
uint8_t shft) { | ||
return __builtin_riscv_cv_alu_subRN(a, b, shft); | ||
} | ||
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static __inline__ unsigned long __DEFAULT_FN_ATTRS | ||
__riscv_cv_alu_subuRN(unsigned long a, unsigned long b, uint8_t shft) { | ||
return __builtin_riscv_cv_alu_subuRN(a, b, shft); | ||
} | ||
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#endif // defined(__riscv_xcvalu) | ||
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#if defined(__cplusplus) | ||
} | ||
#endif | ||
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#endif // define __RISCV_COREV_ALU_H |
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Did the intrinsics keep the 't' in their name even though the instruction was renamed here openhwgroup/cv32e40p#833?
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I will update the intrinsics accordingly after the documentation is renamed.
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I would rather see them deleted. If it's possible to rename them then it's possible to remove them outright and require people to write the trivial standard C equivalent. They serve zero purpose that I can see.