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Jul 27, 2024
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[NFC][VectorCombine] Add negative sanitizer tests #100832

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[𝘀𝗽𝗿] initial version
vitalybuka Jul 26, 2024
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vitalybuka Jul 26, 2024
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52 changes: 52 additions & 0 deletions llvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -626,6 +626,58 @@ define <8 x i16> @gep1_load_v2i16_extract_insert_v8i16(ptr align 1 dereferenceab
ret <8 x i16> %r
}

; Negative sanitizer tests.

define <4 x i32> @load_i32_insert_v4i32_asan(ptr align 16 dereferenceable(16) %p) nofree nosync sanitize_address {
; CHECK-LABEL: @load_i32_insert_v4i32_asan(
; CHECK-NEXT: [[S:%.*]] = load i32, ptr [[P:%.*]], align 4
; CHECK-NEXT: [[R:%.*]] = insertelement <4 x i32> poison, i32 [[S]], i32 0
; CHECK-NEXT: ret <4 x i32> [[R]]
;
%s = load i32, ptr %p, align 4
%r = insertelement <4 x i32> poison, i32 %s, i32 0
ret <4 x i32> %r
}

define <4 x float> @load_v2f32_extract_insert_v4f32_hwasan(ptr align 16 dereferenceable(16) %p) nofree nosync sanitize_hwaddress {
; CHECK-LABEL: @load_v2f32_extract_insert_v4f32_hwasan(
; CHECK-NEXT: [[L:%.*]] = load <2 x float>, ptr [[P:%.*]], align 4
; CHECK-NEXT: [[S:%.*]] = extractelement <2 x float> [[L]], i32 0
; CHECK-NEXT: [[R:%.*]] = insertelement <4 x float> poison, float [[S]], i32 0
; CHECK-NEXT: ret <4 x float> [[R]]
;
%l = load <2 x float>, ptr %p, align 4
%s = extractelement <2 x float> %l, i32 0
%r = insertelement <4 x float> poison, float %s, i32 0
ret <4 x float> %r
}

define <4 x float> @load_v2f32_extract_insert_v4f32_tsan(ptr align 16 dereferenceable(16) %p) nofree nosync sanitize_thread {
; CHECK-LABEL: @load_v2f32_extract_insert_v4f32_tsan(
; CHECK-NEXT: [[L:%.*]] = load <2 x float>, ptr [[P:%.*]], align 4
; CHECK-NEXT: [[S:%.*]] = extractelement <2 x float> [[L]], i32 0
; CHECK-NEXT: [[R:%.*]] = insertelement <4 x float> poison, float [[S]], i32 0
; CHECK-NEXT: ret <4 x float> [[R]]
;
%l = load <2 x float>, ptr %p, align 4
%s = extractelement <2 x float> %l, i32 0
%r = insertelement <4 x float> poison, float %s, i32 0
ret <4 x float> %r
}

; Double negative msan tests, it's OK with the optimization.

define <2 x float> @load_f32_insert_v2f32_msan(ptr align 16 dereferenceable(16) %p) nofree nosync sanitize_memory {
; CHECK-LABEL: @load_f32_insert_v2f32_msan(
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[P:%.*]], align 16
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <2 x i32> <i32 0, i32 poison>
; CHECK-NEXT: ret <2 x float> [[R]]
;
%s = load float, ptr %p, align 4
%r = insertelement <2 x float> poison, float %s, i32 0
ret <2 x float> %r
}

; PR30986 - split vector loads for scalarized operations
define <2 x i64> @PR30986(ptr %0) {
; CHECK-LABEL: @PR30986(
Expand Down
80 changes: 80 additions & 0 deletions llvm/test/Transforms/VectorCombine/X86/load-widening.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -382,3 +382,83 @@ define <4 x i32> @load_v2i32_v4i32_addrspacecast(ptr addrspace(5) align 16 deref
%s = shufflevector <2 x i32> %l, <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x i32> %s
}

; Negative-negative tests with msan, which should be OK with widening.

define <4 x float> @load_v1f32_v4f32_msan(ptr dereferenceable(16) %p) sanitize_memory {
; CHECK-LABEL: @load_v1f32_v4f32_msan(
; CHECK-NEXT: [[S:%.*]] = load <4 x float>, ptr [[P:%.*]], align 16
; CHECK-NEXT: ret <4 x float> [[S]]
;
%l = load <1 x float>, ptr %p, align 16
%s = shufflevector <1 x float> %l, <1 x float> poison, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
ret <4 x float> %s
}

; Negative tests with sanitizers.

define <4 x float> @load_v1f32_v4f32_asan(ptr dereferenceable(16) %p) sanitize_address {
; CHECK-LABEL: @load_v1f32_v4f32_asan(
; CHECK-NEXT: [[L:%.*]] = load <1 x float>, ptr [[P:%.*]], align 16
; CHECK-NEXT: [[S:%.*]] = shufflevector <1 x float> [[L]], <1 x float> poison, <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: ret <4 x float> [[S]]
;
%l = load <1 x float>, ptr %p, align 16
%s = shufflevector <1 x float> %l, <1 x float> poison, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
ret <4 x float> %s
}

define <4 x float> @load_v2f32_v4f32_hwasan(ptr align 16 dereferenceable(16) %p) sanitize_hwaddress {
; CHECK-LABEL: @load_v2f32_v4f32_hwasan(
; CHECK-NEXT: [[L:%.*]] = load <2 x float>, ptr [[P:%.*]], align 1
; CHECK-NEXT: [[S:%.*]] = shufflevector <2 x float> [[L]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: ret <4 x float> [[S]]
;
%l = load <2 x float>, ptr %p, align 1
%s = shufflevector <2 x float> %l, <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x float> %s
}

define <4 x float> @load_v3f32_v4f32_tsan(ptr dereferenceable(16) %p) sanitize_thread {
; CHECK-LABEL: @load_v3f32_v4f32_tsan(
; CHECK-NEXT: [[L:%.*]] = load <3 x float>, ptr [[P:%.*]], align 1
; CHECK-NEXT: [[S:%.*]] = shufflevector <3 x float> [[L]], <3 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
; CHECK-NEXT: ret <4 x float> [[S]]
;
%l = load <3 x float>, ptr %p, align 1
%s = shufflevector <3 x float> %l, <3 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
ret <4 x float> %s
}

define <8 x float> @load_v2f32_v8f32_hwasan(ptr dereferenceable(32) %p) sanitize_hwaddress {
; CHECK-LABEL: @load_v2f32_v8f32_hwasan(
; CHECK-NEXT: [[L:%.*]] = load <2 x float>, ptr [[P:%.*]], align 1
; CHECK-NEXT: [[S:%.*]] = shufflevector <2 x float> [[L]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: ret <8 x float> [[S]]
;
%l = load <2 x float>, ptr %p, align 1
%s = shufflevector <2 x float> %l, <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
ret <8 x float> %s
}

define <4 x i32> @load_v2i32_v4i32_asan(ptr dereferenceable(16) %p) sanitize_address {
; CHECK-LABEL: @load_v2i32_v4i32_asan(
; CHECK-NEXT: [[L:%.*]] = load <2 x i32>, ptr [[P:%.*]], align 1
; CHECK-NEXT: [[S:%.*]] = shufflevector <2 x i32> [[L]], <2 x i32> poison, <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: ret <4 x i32> [[S]]
;
%l = load <2 x i32>, ptr %p, align 1
%s = shufflevector <2 x i32> %l, <2 x i32> poison, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
ret <4 x i32> %s
}

define <4 x i32> @load_v2i32_v4i32_non_canonical_mask_commute_hwasan(ptr dereferenceable(16) %p) sanitize_hwaddress {
; CHECK-LABEL: @load_v2i32_v4i32_non_canonical_mask_commute_hwasan(
; CHECK-NEXT: [[L:%.*]] = load <2 x i32>, ptr [[P:%.*]], align 1
; CHECK-NEXT: [[S:%.*]] = shufflevector <2 x i32> poison, <2 x i32> [[L]], <4 x i32> <i32 2, i32 3, i32 poison, i32 poison>
; CHECK-NEXT: ret <4 x i32> [[S]]
;
%l = load <2 x i32>, ptr %p, align 1
%s = shufflevector <2 x i32> poison, <2 x i32> %l, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
ret <4 x i32> %s
}
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